循序性側向結晶技術能有效增大複晶矽的晶粒尺寸及控制晶粒邊界的位置，以提升低溫複晶矽薄膜電晶體的性能。然而，由於循序性側向結晶和一般雷射結晶技術，所成長之晶粒型態不同，循序性側向結晶製程形成與通道長度方向平行之晶粒邊界，將影響元件之可靠度。本論文將探討hot carrier stress對於循序性側向結晶技術之複晶矽薄膜電晶體所造成的影響。由實驗結果顯示，經stress作用後，元件特性的衰退現象和其通道寬度有關。針對此結果，本篇論文提出一全新的衰退機制及電路模型來模擬其衰退行為，以充分預估元件特性在電路操作下的變化。

Sequential lateral solidification (SLS) technology developed for crystallizing amorphous Si enlarges grain size and controls the position of grain boundaries effectively. However, thin-film transistors made by SLS suffer reliability issues possibly due to the innate sub-grain boundaries parallel to the drain current direction as a result of this unique solidification process. In this thesis, we observed channel-width-dependent degradation on these devices after hot carrier stress. A degradation model was proposed and verified by comparing the measured characteristic with the simulated behavior on the proposed sub-circuit, which successfully explains the degraded transistor behavior and its width dependence.

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