隨著超大型積體電路的演進，製程技術逐漸縮至28奈米甚至20奈米，後段製程的金屬連接線的尺寸也因此跟著縮小，這樣的趨勢正是為了滿足摩爾定律，使半導體產業能夠持續的發展下去。後段製程的金屬連接線的尺寸與距離也隨之縮小，會使得電路中的寄生效應就更加的不可忽視。寄生效應會影響電路的訊號完整度，在訊號的傳遞當中金屬連接線所產生的寄生電阻、寄生電容與寄生電感會對整體電路有不良的影響。當工作頻率不斷的提高，如何去精確的估計與模擬後段金屬連接線的寄生效應是很重要的議題。

在這篇論文，首先使用電磁模擬軟體SONNET，根據不同層的訊號線和參考平面的測試結構，抽取其散射參數。然後在使用方程式將散射參數(S-Parameters)轉成寄生電阻(R)、寄生電感(L)、寄生電容(C)與寄生電導(G)。同時將RLCG這四種參數，可以建立不同的傳輸線的時域模型，如RC、RLC及RLCG。最後利用HSPICE將時域模型轉換成散射參數作為驗證。

最後實作一個圖形化介面的軟體，提供兩種模式方便使用者使用，減少設計電路的時間。在第一模式中，使用者輸入頻率、寬度、長度與測試結構產生RLCG的值與特性阻抗(Z0)。在第二模式中，程式讀取各頻率對散射參數的資料，產生時域參數的資料庫與RLCG對應頻率的關係圖。

As the evolution of VLSI circuits, manufacturing technology is gradually reduced to 28nm or even 20nm and Back End Of Line (BEOL) metal interconnect wire size is also shrunk to follow Moore’s Law to help the semiconductor industry developing. Shrinking size of BEOL metal Interconnect wire makes the circuit parasitic effect become more significant. Parasitic effects, including resistance, capacitance, and inductance degrade the signal integrity of circuits. Therefore, while the operating frequency keeps increasing to new levels, it is critical to know how to accurate estimate and simulate parasitic effects of BEOL metal interconnect wire.

In this thesis, firstly, we use electromagnetic field solver software, SONNET, to extract the scatter parameters by different layers of the signal line and the reference plane of the test structures. Then, the methodology adopted in this research is using formula to transform scatter parameters into RLCG, which is four parameters: resistance (R), Inductance (L), capacitance (C) and conductance (G). Meanwhile, various combinations of the four parameters: RLCG can also establish different time-domain models of transmission line, such as RC, RLC and RLCG. Also, we use HSPICE to transform time-domain model into scatter parameters, which can be applied to verify scatter parameter and time-domain model.

Finally, we implement a graphical interface software which offers two modes to help users to save time for circuit design. One of the modes is that users input operating frequency, width, length and test structure of wire, and then RLCG values and characteristic impedance (Z0) will be generated. Another mode is program reading data from frequency with scatter parameters, and libraries and graph and the values of RLCG with frequency will be generated.

[1] Intel Corporation, "Moore's Low Inspires Intel Innovation".
Available at http://www.nano-ou.net/Edu2ImagePages/Moores.aspx
[2] Ching-Yang Yan, "Proposing A New Fast 3D Electromagnetic-based RLC Exttraction Software Platform for 3D-IC and System-in-Package Designs," in M.S Dissertation, Department of Computer Science, Nation Tsing Hua University, Taiwan, 2009.
[3] Han-Yu Tsai, "Modeling and Validating Time-Domain and Frequency-Domain Transmission Line Parameters," in M.S Dissertation, Department of Electronic Engineering, Nation Tsing Hua University, Taiwan, 2011.
[4] T. Sakurai and K. Tamaru, “Simple Formula for Two- and Three-Dimension Capacitances,” IEEE Trans. Electron Devices, pp. 183-185, Feb 1983.
[5] David M. Pozar, "MICROWAVE ENGINEEGING Third Edition," WILEY, pp. 174-182, 2005.
[6] M. A. Plonus, "Applied Electromagnetics," McGraw-Hill, pp. 553-571, 1978.
[7] Keh-Jeng Chang, Tsun-Ming Wu and Ming-Jin Huang, "Three-dimensional electromagnetic modeling of system-in-package and system-on-glass transmission-line parameters for DFM," 2008.
[8] Sonnet Software Inc, SONNET User's Guide, 2007.
[9] Meng-Hung Shen, Chieh-Hung Cheng and Po-Chiun Huang, “HSPICE Introduction,” NTHU LaRC, 2010.
[10] David M. Pozar, “MICROWAVE ENGINEEGING Third Edition,” WILEY, pp. 57-64, 2005.

[11] W. R. Eisenstadt and Y. Eo, “S-parameter-based IC interconnect transmission line characterization,” IEEE Trans. Comp., Hybrids, Manufact. Technol., pp. 483-490, Aug 1992.
[12] Yungseon Eo and William R. Eisenstadt, “High-speed VLSI interconnect modeling based on S-parameter measurements,” IEEE Trans. Comp., Hybrids, Manufact. Technol., VOL 15, NO 4, August 1993.
[13] Dongchul Kim and Yungseon Eo, “S-parameter-measurement-based time-domain signal transient and crosstalk noise characterization of coupled transmission lines,” IEEE Trans. Adv. Packag., VOL. 32, NO. 1, February 2009.
[14] SYNOPSYS, HSPICE User Guide: RF Analysis, 2010.
[15] Keh-Jeng Chang, Soo-Young Oh, and Ken Lee, “HIVE: An Efficient Interconnect Capacitance Extractor to Support Submicron Multilevel Interconnect Designs,” IEEE ICCAD, pp. 294-297, 1991.
[16] Keh-Jeng Chang, Norman H. Chang, Soo-Young Oh, and Ken Lee, “Parameterized SPICE subcircuits for submicron multilevel interconnect modeling,” IEEE VLSI Technology, pp. 78-79, June 1992.