H.264/AVC運動估測及殘餘重建架構設計與分析｜國立清華大學博碩士論文庫

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研究生：	趙學德 Hsueh-Te Chao
論文名稱：	H.264/AVC運動估測及殘餘重建架構設計與分析 Design and Analysis of Architecture for H.264/AVC Motion Estimation and Residual Reconstruction
指導教授：	陳永昌 Yung-Chang Chen
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2005
畢業學年度：	93
語文別：	英文
論文頁數：	64
中文關鍵詞：	H.264 、運動估測、殘餘重建、低功率
外文關鍵詞：	H.264, Motion Estimation, Residual Reconstruction, low power
相關次數：	點閱：2 下載：0
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H.264/AVC 是目前最新的壓縮標準，相較於現今的壓縮標準，H.264在傳輸量的節省與編碼失真的控制上都有顯著的改善，但是它的複雜編碼處理使得即時編碼應用的可行性不受到保證，以及龐大的運算量會造成嚴重的功率消耗，因此H.264 將面臨極大的挑戰，縱使擁有優秀的效能，但在謹慎的觀點下會使它無法普遍應用。
本論文首要目標是最佳化H.264運動估測架構與降低其運算複雜度，我們基於低功率演算法來實現H.264運動估測架構，設計彈性化的架構以利輕易的重組來符合各種應用的需求，且同時擁有即時編碼能力。
此外，我們提出了低複雜度的H.264重建架構，它能同時產生重排係數及恢復重建畫面，最後我們採用3階段pipeline策略提出了baseline編碼架構，它能對特定階段處理做有效的整合及管理。
我們利用Xilinx FPGA平台實驗驗證架構即時處理能力，根據架構模擬結果，可觀察到1/4畫點精練可使整數畫點的運動補償PSNR提升約3dB，及運用低功率策略在不損失原有品質下，可使H.264運動估測架構實質上省下超過70%的功率消耗，最後baseline編碼器能使彩色重建畫面保持固定45dB，基本上確保了解碼器能顯示穩定品質的畫面。

H.264/AVC is the latest video compression standard. It achieves a significant improvement in bit-rate saving and rate-distortion performance compared with all existing compression standards. However, H.264 complicated encoding process can not guarantee feasibility in real-time coding implementation; in addition, huge computation will cause huge power-consumption. Therefore, from a conservative view, it will face a big challenge for becoming unpopular even it has superior performance.
The object of this thesis is to optimize the architectures of H.264 motion estimation and to reduce its computational complexity. The architecture of H.264 motion estimation is based on low-power algorithm. Flexible architecture is designed such that the use of H.264 in different applications can be adjusted by easy-recombining, and it will also possess real-time coding capability.
In addition, we propose a H.264 reconstruction architecture with low-complexity, which produces the reordering coefficients and rebuilds reconstructed frame respectively. Finally, we propose baseline encoder architecture with three-stage pipeline scheme, which effectively incorporates and manages specific stages for real-time coding.
Xilinx FPGA platform simulation demonstrates the real-time capability of proposed H.264 ME architecture. From architecture simulation, we observe that integer motion compensation PSNR could be improved about 3 dB by quarter-pixel refinement. And proposed low-power strategies for motion estimation architecture could substantially save power over 70% without losing original quality. Finally, the proposed baseline encoder architecture rebuilds color reconstruction frame with constant quality of 45dB basically and ensures that decoder displays stable decoding frame.

Chapter 1: Introduction 1
1 H.264 is the future 1
2 Motivation 1
3 Thesis organization 2
Chapter 2: Overview of H.264/AVC 3
1 Major features in H.264/AVC 3
2 H.264/AVC encoding process 5
3 H.264/AVC motion estimation 6
4 H.264/AVC integer transform 9
5 H.264/AVC quantization 10
Chapter 3: H.264/AVC motion estimation and reconstruction   architecture 13
1 Three stage MB pipeline    13
2 H.264 Motion compensation stage 14
2.1 Current line buffer management    15
2.2 SR buffer management 16
2.3 Two-field search algorithm for H.264 motion estimation 17
2.4 PE    19
2.5 2D PE module     20
2.6 Find MV module 21
2.7 Segment Decision module 22
2.8 H.264 integer-pixel motion estimation architecture 24 3.2.9 Sub-pixel interpolation flow in SR buffer 25       3.2.10 Half-pixel refinement module 27
2.11 H.264 half-pixel motion estimation architecture    28
2.12 Quarter-pixel refinement module 29
2.13 H.264 quarter-pixel motion estimation architecture 30
2.14 H.264 motion estimation low-power design 32
2.15 Low-power mask algorithm 33
2.16 Low-power mask module 34
2.17 Low-power PE 35
2.18 H.264 motion estimation architecture with low-power mask 36
2.19 Skip Decision hardware-oriented Algorithm 37        3.2.20 H.264 motion estimation with skip decision architecture 38
3 H.264 Reconstruction Stage 40
3.1 4x4 integer transform module 41
3.2 4x4 quantization module 42
3.3 4x4 inverse quantization module 43
3.4 4x4 integer inverse transform module 44
3.5 Reorder module 45
3.6 H.264 Reconstruction architecture 46
4 H.264/AVC baseline encoder architecture 47
Chapter 4: Simulation Result 49
1 Algorithm simulation for H.264 MC and partition 49
2 Algorithm simulation for H.264 ME with skip decision 51
3 Architecture simulation for H.264 ME in integer/half/quarter-pixel 55
4 Architecture simulation for H.264 ME with low-power design 56
5 Architecture simulation for H.264 reconstruction 57
6 Xilinx FPGA simulation for real-time H.264 ME 58
Chapter 5: Conclusions and Future Works 61
1 Conclusions 61
2 Future works 62
References 63

                                

[1] ThomasWiegand, Gary J. Sullivan, Gisle Bjøntegaard, and Ajay Luthra, “Overview of the H.264/AVC Video Coding Standard”, IEEE Transactions on Circuits and Systems for Video Ttechnology, Vol. 13, No. 7, July 2003.
[2] Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification (ITU-T Rec. H.264 | ISO/IEC 14496-10 AVC).
[3] Thomas Komarek and Peter Pirsch, “Array Architecture for Block Matching Algorithms”, IEEE Transactions on Circuits and Systems, Vol.36, No.10, October 1989.
[4] Seung Hyun Nam, Jong Seob Baek, Moon Key Lee, “Flexible VLSI Architecture of Full Search Motion Estimation for Video Application”, IEEE Transactions on Consumer Electronics, Vol. 40, No. 2, MAY 1994.
[5] Swee Yeow Yap and John V.McCanny, “A VLSI Architecture for Variable Block Size Video Motion Estimation”, IEEE Transactions on Circuits and Systems, Vol. 51, No. 7, JULY 2004.
[6] Yu-Wen Huang, Tu-Chih Wang, Bing-Yu Hsieh, and Liang-Gee Chen, “Hardware Architecture Design for Variable Block Size Motion Estimation in MPEG-4 AVC/JVT/ITU-T H.264”, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03 Volume 2, 25-28 May 2003.
[7] Tung-Chien Chen, Yu-Wen Huang, and Liang-Gee Chen, “Fully Utilized and Reusable Architecture for Fractional Motion Estimation of H.264/AVC”, IEEE International Conference on ICASSP '04 Volume 5, 17-21 May 2004.
[8] Hsien-Wen Cheng; Lan-Rong Dung, “A Vario-Power ME Architecture Using Content-Based Subsample Algorithm”, IEEE Transactions on Consumer Electronics, Volume 50, Issue 1, Feb 2004.
[9] Kun-Bin Lee, Hao-Yun Chin, Hui-Cheng Hsu, Chein-Wei Jen, “QME: an efficient subsampling-based block matching algorithm for motion estimation” , Proceedings of the 2004 International Symposium on Circuits and Systems, 2004. ISCAS '04 Volume 2, 23-26 May 2004.
[10] Malvar, H.S., Hallapuro, A., Karczewicz, M., Kerofsky, L., “Low-complexity transform and quantization in H.264/AVC” , IEEE Transactions on Circuits and Systems for Video Technology, Volume 13, Issue 7, July 2003.
[11] Tu-Chih Wang, Yu-Wen Huang, Hung-Chi Fang, Liang-Gee Chen, “Parallel 4/spl times/4 2D transform and inverse transform architecture for MPEG-4 AVC/H.264”, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03 Volume 2, 25-28 May 2003.
[12] Kordasiewicz, R., Shirani, S., “Hardware implementation of the optimized transform and quantization blocks of H.264”, Canadian Conference on Electrical and Computer Engineering, 2004.Volume 2, 2-5 May 2004.
[13] Tung-Chien Chen, Yu-Wen Huang, Liang-Gee Chen, “Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture”, Proceedings of the 2004 International Symposium on Circuits and Systems, 2004. ISCAS'04 Volume 2, 23-26 May 2004.
[14] Demin Wang; Labit, C.; Ronsin, J., “Segmentation-based motion-compensated video coding using morphological filters”, IEEE Transactions on Circuits and Systems for Video Technology, Volume 7, Issue 3, June 1997.
[15] Xilinx, “Virtex-II Platform FPGA User Guide”, UG002 (v1.4) 1 November 2002.
[16] Xilinx, “Platform Specification Format Reference Manual”, UG131 (v1.0) August 20, 2004.

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