電子封裝(Electronic Packaging)朝向微型化方向發展，三維晶片整合(3D IC Integration)封裝和傳統封裝相比，除體積較小外，較少訊號延遲(Signal Delay)更是一大突破，近年已逐漸使用在攜帶式電子產品中。攜帶式電子產品因尺寸較小而易於使用過程中掉落，因此須研究其封裝元件掉落可靠度以增加產品壽命。儘管三維晶片整合封裝已發展了許多之製程技術及結構，但其掉落可靠度研究仍有所不足。
電路板層級掉落測試(Board Level Drop Test)被廣泛採用以評估封裝受掉落衝擊時之可靠度。本研究運用有限單元軟體ANSYS/LS-DYNA 3D進行了電路板層級掉落模擬，並搭配實驗結果以驗證方法之可信賴度。接著利用該模擬方法分析三維晶片整合封裝之動態行為。最終以參數化分析探討封裝尺寸、材料等可能變異對可靠度之影響。掉落測試結果顯示與熱循環測試情況不同，晶片堆疊層數增加會導致封裝銅凸塊掉落可靠度下降。添加底膠可提升錫球之可靠度，但在矽載板過薄之情況下會導致銅凸塊可靠度下降。

關鍵字：三維晶片整合封裝、電路板層級掉落測試。

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