一個十一位元每秒一億五千萬次取樣次階連續漸進式類比數位轉換器

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研究生：	林瑁陞 Lin, Mao-Sheng
論文名稱：	一個十一位元每秒一億五千萬次取樣次階連續漸進式類比數位轉換器 A 11-Bit 150MS/s Subrange Successive-Approximation Register Analog-to-Digital Converter
指導教授：	朱大舜 Chu, Ta-Shun 彭朋瑞 Peng, Pen-Jui
口試委員:	王毓駒 Wang, Yu-Jiu 吳仁銘 Wu, Jen-Ming
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2023
畢業學年度：	111
語文別：	中文
論文頁數：	86
中文關鍵詞：	連續漸進式類比數位轉換器、次階連續漸進式類比數位轉換器、冗餘位元、偵測省略切換法
外文關鍵詞：	SAR ADC, Subrange SAR ADC, Redundancy, Detect-And-Skip switching
相關次數：	點閱：50 下載：0
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本論文探討如何實現一個11位元每秒一億五千萬次取樣的連續漸進式類比數位轉換器。使用的製程為台積電T65製程，架構上採用了次階式(Subrange)的概念，分成了粗略類比數位轉換器以及精確類比數位轉換器，由於粗略類比數位轉換器可以有更高的轉換速度，可以透過粗略類比數位轉換器更快速的解析出高位元組(MSBs)，加速整體轉換速率，並加入偵測省略切換演算法技術(Detect-And-Skip)，可以減少精確電容陣列的切換次數，來降低其切換功率消耗。在數位控制邏輯中，將傳統的暫存器改以栓鎖器實現，可以減少比較輸出至切換的傳遞延遲時間，省下一個暫存器延遲時間，並採用具錯誤補償的二進位演算法來修正粗略類比數位轉換器與精確類比數位轉換器之間的誤差。在1.2V的供應電壓，150MHz取樣頻率，輸入頻率為74.41MH情況，其模擬結果為功率消耗為2.094mW，有效位元(ENOB)為10.59bit，訊號失真比(SNDR)約為65.5 dB，電路面積約0.0837(mm2)。

This thesis discusses how to implement a Successive-Approximation-Register analog-to-digital converter (ADC) that samples at a rate of 150 million samples per second with 11-bit resolution. The process is TSMC T65 technology. The architecture employs a sub-ranging approach, dividing the ADC into a coarse analog-to-digital converter (Coarse ADC) and a fine analog-to-digital converter (Fine ADC). Due to the higher conversion speed of Coarse ADC, they can extract the MSBs faster, thereby accelerating the overall conversion speed. Additionally, by incorporating the Detect-And-Skip algorithm, the number of capacitor switching in fine conversions is reduced, which in turn reduces power consumption. In the digital control logic, registers are replaced with latches to reduce the propagation delay from the comparator outputs to the switches. A binary search with error compensation is used to correct the mismatch between coarse and fine conversions. At a supply voltage of 1.2V and a sampling frequency of 150MHz, for an input frequency of 74.41MHz, the simulation results are as follows: power consumption is 2.094mW, effective number of bits (ENOB) is 10.59 bits, signal-to-noise and distortion ratio (SNDR) is 65.5 dB, and the circuit area is 0.0837 mm².

摘要 i
ABSTRACT ii
目錄 iii
圖目錄 viii
表目錄 xiv
第一章 簡介 1
1 研究動機 1
2 論文章節組織 2
第二章 研究背景以及相關研究介紹 3
1 類比數位轉換器分類 3
2 類比數位轉換器專有名詞介紹 5
2.1 取樣與量化 5
2.2 取樣率(Sampling Rate) 6
2.3 奈奎斯定理(Nyquist criterion) 6
2.4 解析度(Resolution) 7
2.5 最小有效位元(Least Signification Bit) 8
2.6 量化誤差(Quantization Error) 8
3 靜態參數 10
3.1 偏移誤差(Offset Error) 10
3.2 增益誤差(Gain Error) 11
3.3 差動非線性度(Differential Nonlinearity) 12
3.4 積分非線性度(Integral Nonlinearity) 13
3.5 遺失碼(Missing Codes) 14
4 動態參數 15
4.1 訊號對雜訊比(Signal-to-Noise Ratio) 15
4.2 訊號對雜訊諧波比(Signal-to-Noise and Distortion Ratio) 16
4.3 有效位元數(Effective Number of Bits) 16
4.4 動態範圍(Dynamic Range) 17
4.5 總諧波失真(Total Harmonic Distortion) 17
4.6 優值 18
第三章 連續漸進式類比數位轉換器運作原理介紹 19
1 架構及原理介紹 19
2 同步與非同步 21
3 電荷重新分配 23
4 切換電容能量計算 24
5 切換演算法 26
5.1 傳統式電容切換演算法(Conventional switching algorithm) 26
5.2 單調性電容切換演算法(Monotonic switching algorithm) 28
5.3 回切式電容切換演算法(Bi-direction switching algorithm) 30
5.4 電容拆半切換演算法(Split-capacitor switching algorithm) 32
5.5 電容切換演算法分析整理 33
6 錯誤容忍與補償校正 35
6.1 傳統二進位搜尋演算法 35
6.2 非二進位搜尋演算法 36
6.3 具錯誤補償二進位搜尋演算法 38
第四章 次階連續漸進式類比數位轉換器分析 40
1 架構原理介紹 40
2 時序分析 41
3 偵測省略演算法(Detect-And-Skip) 43
4 次階連續漸進式架構的非理想效應 46
4.1 取樣相異誤差 46
4.2 電容增益相異誤差 48
4.3 比較器偏移相異誤差 50
第五章 十一位元次階類比數位轉換器設計 52
1 十一位元次階類比數位轉換器主架構 52
2 取樣保持電路 53
2.1 電路原理 53
2.2 設計考量 54
2.3 電路實作 59
2.4 模擬結果 62
3 電容矩陣設計 63
3.1 雜訊考量 63
3.2 不匹配考量 63
3.3 電容權重設計 64
3.4 電容佈局規劃 66
4 比較器 67
4.1 電路實作 68
4.2 模擬結果 70
5 數位控制邏輯 73
5.1 時脈邏輯產生電路 73
5.2 邏輯控制電路 75
6 數位校正電路(ADEC) 78
7 電路佈局及效能模擬 79
7.1 電路佈局規劃 79
7.2 動態參數模擬 80
7.3 功耗分析與模擬結果總結 82
第六章 結論與未來展望 84
參考資料 85

                                

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