採用多種工作電壓（multiple-supply voltages）在單晶片系統（System-on-Chip）的設計上是一條實現低功率的有效途徑。實體設計（physical design）流程中，在平面規劃（floorplanning）階段考量多種工作電壓的問題是最適當的。過去有許多方法將此問題分成設定工作電壓（voltage assignment）的問題以及平面規劃的問題。這篇論文中，我們提出了一個利用模擬退火法（simulated annealing）來考量電壓島（voltage island）佈局的平面規劃，以同時解決這兩個問題。我們的方法使用可以有效率地在模擬退火時評估電源耗費的 Corner Block List [1] 作為平面規劃的表示法。實驗結果顯示，我們的演算法可在一個平面規劃中產生平均約三個電壓島，並減少 31.63% 的電力消耗。與過去的方法 [2] 相比，我們的方法可以得到較少的閒置空間（deadspace）、總線長（total wirelength）、電源消耗以及電位移轉器（level shifter）的數量。

Reducing power consumption is an significant issue in modern System-on-Chip designs. Multiple-supply voltages (MSV's) design is one of the effective ways for dynamic power reduction, and floorplanning is the appropriate stage in the physical design cycle for applying MSV's design. Previous works have addressed the MSV's design problem at floorplanning stage by solving the voltage assignment problem and the floorplanning problem separately. In this thesis, we propose a simulated annealing (SA) based voltage island-aware floorplanning algorithm to solve the two problems simultaneously. Our algorithm is based on corner block list [1] which is efficient for integrating the evaluation process of power costs function into SA. Experimental results show that our algorithm could save 31.63\% total power consumption by forming three voltage islands in average. We could obtain better deadspace, total wirelength and power consumption than the previous work [2] as well.

[1] X. Hong, G. Huang, Y. Cai, J. Gu, S. Dong, C. K. Cheng, and J. Gu, “Corner block list: an effective and efficient topological representation of non-slicing floorplan,” in IC-CAD ’00: Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, pp. 8–12, 2000.
[2] Q. Ma and E. F. Y. Young, “Voltage island-driven floorplanning,” in ICCAD ’07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, pp. 644–649, 2007.
[3] G. E. Moore, Cramming more components onto integrated circuits. Electronics, 1965.
[4] S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi, Optimization by Simulated Annealing, vol. 220. Science, 1983.
[5] D. E. Lackey, P. S. Zuchowski, T. R. Bednar, D. W. Stout, S. W. Gould, and J. M. Cohn, “Managing power and performance for System-on-Chip designs using Voltage Islands,” in ICCAD ’02: Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, pp. 195–202, 2002.
[6] A. U. Diril, Y. S. Dhillon, A. Chatterjee, and A. D. Singh, “Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages,” 42in VLSID ’05: Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design, pp. 159–164, 2005.
[7] R. H. Otten, “Automatic floorplan design,” in DAC ’82: Proceedings of the 19th conference on Design automation, pp. 261–267, 1982.
[8] D. F. Wong and C. L. Liu, “A new algorithm for floorplan design,” in DAC ’86: Proceedings of the 23rd ACM/IEEE conference on Design automation, pp. 101–107, 1986.
[9] S. Nakatake, K. Fujiyoshi, H. Murata, and Y. Kajitani, “Module placement on BSG-structure and IC layout applications,” in ICCAD ’96: Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, pp. 484–491, 1996.
[10] H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, “Rectangle-packing-based module placement,” in ICCAD ’95: Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, pp. 472–479, 1995.
[11] J.-M. Lin and Y.-W. Chang, “TCG: a transitive closure graph-based representation for non-slicing floorplans,” in DAC ’01: Proceedings of the 38th conference on Design automation, pp. 764–769, 2001.
[12] P.-N. Guo, C.-K. Cheng, and T. Yoshimura, “An O-tree representation of non-slicing floorplan and its applications,” in DAC ’99: Proceedings of the 36th ACM/IEEE conference on Design automation, pp. 268–273, 1999.
[13] Y.-C. Chang, Y.-W. Chang, G.-M. Wu, and S.-W. Wu, “B*-Trees: a new representation for non-slicing floorplans,” in DAC ’00: Proceedings of the 37th conference on Design automation, pp. 458–463, 2000.
[14] H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, “VLSI module placement based on rectangle-packing by the sequence-pair,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 15, pp. 1518–1524, Dec 1996.
[15] X. Tang, R. Tian, and D. F. Wong, “Fast evaluation of sequence pair in block placement by longest common subsequence computation,” in DATE ’00: Proceedings of the conference on Design, automation and test in Europe, pp. 106–111, 2000.
[16] X. Tang and D. F. Wong, “FAST-SP: a fast algorithm for block placement based on sequence pair,” in ASP-DAC ’01: Proceedings of the 2001 conference on Asia South Pacific design automation, pp. 521–526, 2001.
[17] W.-K. Mak and J.-W. Chen, “Voltage Island Generation under Performance Requirement for SoC Designs,” in ASP-DAC ’07: Proceedings of the 2007 conference on Asia South Pacific design automation, pp. 798–803, 2007.
[18] W.-P. Lee, H.-Y. Liu, and Y.-W. Chang, “An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning,” in ICCAD ’07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, pp. 650–655, 2007.
[19] D. Sengupta and R. Saleh, “Application-driven floorplan-aware voltage island design,” in DAC ’08: Proceedings of the 45th annual conference on Design automation, pp. 155–160, 2008.
[20] J. Hu, Y. Shin, N. Dhanwada, and R. Marculescu, “Architecting voltage islands in core-based system-on-a-chip designs,” in ISLPED ’04: Proceedings of the 2004 international symposium on Low power electronics and design, pp. 180–185, 2004.
[21] M.-C. Lu, M.-C. Wu, H.-M. Chen, and H.-R. Jiang, “Performance Constraints Aware Voltage Islands Generation in SoC Floorplan Design,” in SOC Conference, 2006 IEEE International, pp. 211–214, Sept. 2006.
[22] S. Zhou, S. Dong, C.-K. Cheng, and J. Gu, “ECBL: an extended corner block list with solution space including optimum placement,” in ISPD ’01: Proceedings of the 2001 international symposium on Physical design, pp. 150–155, 2001.
[23] T.-C. Chen and Y.-W. Chang, “Modern floorplanning based on fast simulated annealing,” in ISPD ’05: Proceedings of the 2005 international symposium on Physical design, pp. 104–112, 2005.