研究生: |
陳彥妤 Yenyu Chen |
---|---|
論文名稱: |
新方法萃取65奈米P型金氧半電晶體的有效電性長度及源極汲極寄生電阻 Extracting the Effective Channel Length and Series Resistance of 65nm pMOSFET |
指導教授: |
龔正
Jeng Gong |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering |
論文出版年: | 2006 |
畢業學年度: | 94 |
語文別: | 英文 |
論文頁數: | 68 |
中文關鍵詞: | 有效長度 、寄生電阻 、速度飽和 、擴散電流 、漏電流 |
外文關鍵詞: | effective channel length, series resistance, velocity saturation, diffusion current, gate leakage current |
相關次數: | 點閱:1 下載:0 |
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在奈米級MOSFET裡有效電性長度異於光罩長度或物理長度甚多,且是spice元件模型裡最重要的參數之一。本論文考慮奈米級MOSFET中,短通道效應、速度飽和效應、寄生電阻與有效長度效應、閘級漏電流效應、擴散電流效應、ballistic transport等影響,重新推倒IV方程式。
本論文改善Shift-and-Ratio Method,從實際量得的數據帶入新推導出更精確的IV方程式,萃取出有效長度與寄生電阻,並與Suciu-Jonston Method、De La Moneda Method、Shift-and-Ratio Method及Gate Leakage Method算出的結果做比較,發現傳統方法萃取出的數值不符合物理意義,唯有我們的新方法能得到合理的值。
本論文在最後簡單討論在P型MOSFET的源極汲極共參雜(co-implant)另一種參雜物的影響。運用新的方法算出有效電性長度及有效寄生電阻在不同製程的差異性,我們發現共參雜氟(fluorine)可以得到最陡峭的接面(abrupt shallow junction)。
A new, more accurate and more reasonable method of determining the MOSFETs effective channel length and source-drain series resistance is presented in this thesis. This method improves shit-and-ratio method and develops a more accurate calculation system. Comparing the extracted values from the Suciu-Johnston method, De La Moneda method, shift-and-ratio method, gate leakage method, and our new method, we prove that our method is the most accurate and reasonable one. Besides, we use this newly developed method to observe the co-implant source/drain effect in a 65nm pMOSFET.
[1] Dieter K. Schroder, ”Semiconductor Material and Device Characterization,”
John Wiley & Sons, 223-237, 1998.
[2] Paul I. Suciu, Ralph L. Johnston, ”Experimental Derivation of the
Source and Drain Resistance of MOS Transistors,” IEEE Trans. Electron
Dev., vol. ED-27, pp. 1846-1847, 1980.
[3] F. H. De La Moneda, H. N. Kotecha, and M. Shatzkes, ”Measurement of
MOSFET Constants,” IEEE Electron Dev. Lett., EDL-3, 10-12, 1982.
[4] Y. Taur, D. S. Zicherman, D. R. Lombardi, P. R. Restle, C. H. Hsu,
H. I. Hanafi, M. R. Wordeman, B. Davari, and G. G. Shahidi, ”A New
’Shift and Ratio’ Method for MOSFET Channel-Length Extraction,”
IEEE Electron Dev. Lett., 13, 267-269, 1992.
[5] Y. Taur, ”MOSFET Channel Length: Extraction and Interpretation,”
IEEE Trans. Electron Dev., vol. 47,160-170, 2000.
[6] K. Terada and H. Muta, ”A NEW Method to Determine Effective MOSFET
Channel Length,” Japan. J. Appl. Phys., 18, 953-959, 1979.
[7] J. G., J. Chern, P. Chang, R. F. Motta, and N. Godinho, ”A New
Method to Determine MOSFET Channel Length,” IEEE Electron Dev.
Lett., EDL-1, 170-173, 1980.
[8] G. Merckel, J. Borell, and N. Z. Cupcea, ”An accurate large-signal MOS
transistor model for use in computer-aided design,” IEEE Trans. Electron
Dev., vol. ED-19, 681-690, 1972.
[9] M. Marin, M. J. Deen, M. de Murcia, P. Llinares, and J.-C. Vildeuil,
”New Method for the Channel-Length Extraction MOSFETs with Sub-
2-nm Gate Oxide” IEEE Electron Dev. Lett., Vol.25, 202-204, 2004.
[10] E.Miranda, ”Method for Extracting series resistance in MOS devices
using Fowler-Nordheim plot,” Electronics Letters, 2004.
[11] N. Yang and J. J. Wortman, ”A study of the effects of tunneling currents
and reliability of sub-2-nm gate oxides on scaled n-MOSFETs,”
Microelectron. Reliab., 41, 37-46, 2001.
[12] Fariborz Assaderaghi, Dennis Sinitsky, Jeffrey Bokor, Ping K. Ko, Henry
Gaw, and Chenming Hu, ”High-Field Transport of Inversion-Layer Electrons
and Holes Including Velocity Overshoot,” IEEE Trans. Electron
Dev., 44, 664-671, 1997.
[13] D. M. Caugley and R. E. Thomas, Proc. IEEE, 55, 2192-2193, 1967.
[14] B. J. Moon, C. K. Park, K. Lee, and M. Shur, ”New short channel
n-MOSFET current-voltage model in strong inversion and unified parameter
extraction technique,” IEEE Trans. Electron Dev., ED-38, 592-
602,1991
[15] B. J. Moon, C. K. Park, K. Rho, K. Lee, M. Shur, and T. A. Fjeldly,
”Analytical Model for p-Channel MOSFET’s,” IEEE Trans. Electron
Dev., ED-38, 2632-2646, 1991.
[16] Charles G. Sodini, Ping-Keung Ku, and John L. Moll, ”The Effect of
High Fields on MOS Device and Circuit Performance,” IEEE Trans.
Electron Dev., EDL-31,1386-1393, 1983.
[17] F. Fang and X. Fowler, ”Hot-electron effects and saturation velocity in
silicon inversion layer,” J. Appl. Phys., 41, 1825, 1969.
[18] L. Ge, J. G. Fossum, and B. Liu, ”Physical Compact Modeling and
Analysis of Velocity Overshoot in Extremely Scaled CMOS Devices and
Circuits,” IEEE Trans. Electron Dev., ED-48, 2074-2080, 2001.
[19] Kunihiro Suzuki, and Tatsuya Usuki, ”Metal Oxide Semiconductor Field
Effect Transistor(MOSFET) Model Based on a Physical High-Field
carrier-Velocity Model,” Japan. J. Appl. Phys., 43, 77-81, 2004.
[20] John R. Hauser, ”A New and Improved Physic-Based Model for Mos
Transistors,” IEEE Trans. Electron Dev., 52, 2640-2647, 2005.
[21] Michael Y. Kwong, Chang-Hoon Choi, Reza Kasnavi, Peter Griffin,
Robert W. Dutton, ”Series Resistance calculation for Source/Drain Extension
Regions Using 2-D Device Simulation,” IEEE Trans. Electron
Dev., 49, 1219-1225.
[22] F. Lime, C. Guiducci, R. Clerc, G. Ghibaudo, C. Leroux, and T. Ernst,
”Characterization of effective mobility by split C(V) technique in NMOSFET
with ultra-thin gate oxides,” Solid State Electronics, 1147-
1153, 2003
[23] O. Tonomura, Y. Shimamoto, K. Torii, M. Hiratani, S. Saito, and J.
Yugami, ”Evaluation of Mobility in the MOSFET With High Leakage
Current,” ICMT, 91-94, 2003.
[24] O. Tonomura, Y. Shimamoto, S. Saito, K. Torii, M. Hiratani, and
J. Yugami, ”Accurate Evaluation of Mobility in High Gate-Leakage-
Current MOSFETs by Using a Transmission-Line Model,” IEEE Trans.
Electron Dev., 51, 1653-1658, 2004.
[25] Jeng-Cherng Jang, and Jeng Gong, ”A Study of Determiin Effective
Channel Length and Series Resistance, and Noise Model Comparison
for Submicron MOSFETs,” NTHU
[26] Michel, A.E., et al., ”Rapid annealing and the anomalous diffusion of
ion implanted boron into silicon.” Appl. Phys. Lett., 50, 416-418, 1987.
[27] Angelucci, R., P. Negrini, and S. Solmi, ”Transient enhanced diffusion of
dopants in silicon induced by implantation damage.” Appl. Phys. Lett.,
49,1468-1470, 1986.
[28] Morehead, F.F. and R.F. Lever, ”Enhanced ”tail” diffusion of phosphorus
and boron in silicon: Self-interstitial phenomena.” Appl. Phys. Lett.,
48, 151-153, 1986.
[29] Fahey, P.M., P.B. Griffin, and J. D. Plummer, ”Point defects and dopant
diffusion in silicon.”, Rev. Mod. Phys., 61, 289-384, 1989.
[30] L. S. Robertson, J. Jacques, K. S. Jones, M. E. Law, D. F. Downey,
M.J. Rendon, and D. Sing, ”Co-implantation of Boron and Fluorine in
Silicon”, Japan Society of Applied Physics, 57-61, 2001.
[31] P. A. Stolk, D. J. Eaglesham, H.-J. Gossmann, and J. M. Poate, ”Carbon
incorporation in silicon for suppressing interstitial-enhanced boron
diffusion”, Appl. Phys. Lett., 66, 1370-1372, 1995.
[32] T. Shano, R. Kim, T. Hirose, Y. Furuta, H. Tsuji, M. Furuhashi, and
K. Tanijuchi, ”Realization of Ultra-shallow junction: Suppressed Boron
Diffusion and Activation by Optimized Fluorine co-implantation”,
IEDM, 821-824, 2001.
[33] J. R. Shih, M. C. Chiang, H. C. Lin, R. Y. Shiue, Yeng Peng and J. T.
Yue, ” N-Feet HCI Reliability Improvement by Nitrogen Interstitialization and Its Mechanism”, IEEE 40th Annual International Reliability
Physics Symposium, 272-277, 2002.