隨著通訊系統和數據處理需求的增加，對高速比較器的需求也不斷提高。在通訊系統中，高速比較器主要功能為進行快速且準確的比較，以支援數位訊號處理、時序控制、數據解碼、相位調整等功能以確保通訊系統的穩定運行和高效性能。在高速應用中的需求主要有高速數據轉換、高頻通訊、高速接口、高速訊號處理、高速時序控制等，以上高速應用中，比較器的速度都扮演著至關重要的角色。
典型的latch-type比較器架構，透過clk訊號控制切換不同phase。在比較出結果前，必須先將比較器的輸出節點電壓拉開一定程度後，latch才會開始進行positive feedback，重置時再將被拉到GND的節點拉回VDD，而這兩項操作都需要完整VDD swing的反應時間，因此若是操作在高頻率clk，典型架構很有可能無法在半個clk週期內將輸出節點的電壓拉開並進行positive feedback以及將被拉到GND的輸出節點成功重置回VDD。
於是，針對這兩項問題，提出一個全新架構的latch-type比較器。由於不再有input pair MOS，而是將訊號直接輸入到latch gate，省掉將輸出節點電壓拉開的時間，並且直接進行positive feedback；另外，也將reset電壓設計為VDD/2，將原先為VDD的reset電壓幅度降至VDD/2，因此所需的reset時間也會減少。此架構也運用電容跨壓無法瞬間改變的特性，使輸入到兩端latch gate的電壓差為原先輸入電壓差的兩倍，因此也可以加快比較速度。

With the increasing demands of communication systems and data processing, the importance of high-speed comparators is growing. High-speed comparators are primarily used for fast and accurate signal comparisons, supporting digital signal processing, timing control, data decoding, phase adjustment, and other functions to ensure the stable and efficient operation of communication systems. In high-speed applications such as high-speed data conversion, high-frequency communication, and high-speed signal processing, the speed of the comparator is critical to system performance.
Typical latch-type comparator architectures operate in phases controlled by a clk signal. Before obtaining a comparison result, the output node voltages must first be sufficiently pulled apart to trigger positive feedback. During the reset phase, the node pulled to GND is restored to VDD. These operations require a full VDD voltage swing, which can be too slow to complete within half a clock cycle in high-frequency operations.
To address these issues, the proposed architecture feeds the input signals directly into the latch gates, which eliminates the need for input MOS devices and reducing the time required to pull apart the output node voltages and enables immediate positive feedback. Additionally, the reset voltage is set to VDD/2, reducing the reset voltage swing and speeding up the reset process. Furthermore, by using the property that the voltage across a capacitor cannot change instantaneously, the voltage difference at the latch gates becomes twice the original input voltage difference, further accelerating the comparison speed.

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