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研究生: 廖婉伶
Liauh, Woan-Ling
論文名稱: 邏輯製程相容雙極性電晶體
The Study of a Novel CMOS-Compatible Bipolar Junction Transistor
指導教授: 金雅琴
King, Ya-Chin
口試委員: 林崇榮
施教仁
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年: 2013
畢業學年度: 101
語文別: 中文
論文頁數: 66
中文關鍵詞: 雙極性電晶體電阻式記憶體
外文關鍵詞: BJT, RRAM
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  • 快閃記憶體是唯一量產的非揮發性半導體儲存技術,且在現今的高科技電子產品市場中,佔有主宰的地位。但是快閃記憶體隨著製程的微縮,將面臨到許多挑戰,諸如氧化層漏電、軟性崩潰以及密度極限等。因此開發新型的非揮發性記憶體,追求更佳的儲存密度、微縮特性和更快的存取速度有其必要性。
    電阻式記憶體是近年來許多記憶體相關研究的焦點,由於它的非揮發性、耐用度佳且容易微縮等優勢,使它成為未來能取代快閃記憶體的候選人之一。本論文提出雙極性電晶體作為用來驅動電阻式記憶體的驅動器,雙極性電晶體有垂直性的雙極性電晶體和水平式矽鍺兩種,前者包括有P+接點的和覆蓋式PLDD接點,其中P+接點的結構又有分射極只佈植I/O NLDD和同時佈植I/O NLDD與Core I/O NLDD兩種;而後者為在28nm製程下的元件,基極寬度可以微縮較小,加上P-type金氧半電晶體材料為矽鍺,可大幅提高增益值。
    相較於金氧半電晶體當驅動器,藉由高增益的雙極性電晶體驅動,立體垂直電阻式記憶體可以節省面積且降低操作電壓,並具有高效且高密度的特性。


    Flash memory is the only non-volatile semiconductor storage technology for mass production, and dominates the market of high-technology electronic products nowadays. However, flash memory suffers from many of challenges with scaling down, such as gate oxide leakage, soft breakdown, density limit, etc. For this reason, it is necessary to develop a new NVM, in order to pursue higher density, scalability and faster access speed.
    Resistive Random Access Memory has become the focus of many memory studies in recent years, it's a candidate as the next-generation NVM for the future, as a result of its strong advantages in scalability, non-volatility, endurance.
    In this study, we discuss the fabrication and architecture of vertical bipolar junction transistor (BJT) and lateral SiGe bipolar junction transistor, fabricated by 65nm and 28nm CMOS logic process without any extra mask. The vertical BJT basically could be extended to two parts: P+ doping and I/O PLDD doping on base pick up structures. The characteristics for different structures of new BJT are presented. The lateral SiGe BJT is composed of PMOS in parallel. It has the advantage of good current gain due to base width could in small size. Finally, the structure of BJT has been successfully demonstrated by measurement result. We believe that it is a very promising solution for future high density and embedded NVM applications.

    摘要 Abstract 致謝 內文目錄 附圖目錄 附表目錄 第一章 導論 1.1 前言 1.2 論文大綱 第二章 電阻式記憶體及其驅動相關文獻回顧 2.1 電阻式記憶體回顧 2.2 電阻式記憶體驅動相關研究 2.2.1 無驅動電晶體之電阻式記憶體 2.2.2 金氧半電晶體驅動之電阻式憶體 2.2.3 二極體驅動之電阻式記憶體 2.2.4 交叉點電阻式記憶體 第三章 元件之設計概念 3.1 PMOSFET 製程簡介 3.2 元件製程步驟 3.3 元件佈局設計 3.3.1 P+接點之NPN 雙極性電晶體之佈局設計 3.3.2 覆蓋式I/O PLDD接點之NPN雙極性電晶體之佈局 3.3.3 水平式矽鍺之PNP雙極性電晶體之佈局 3.4 垂直雙極性電晶體與水平式矽鍺雙極性電晶體之特色與優勢 3.5 小結 第四章 元件之量測結果與特性分析 4.1 直流量測方法 4.2 P+接點之NPN雙極性電晶體 4.2.1 I/O NLDD 之射極佈值 4.2.2 Core NLDD 與 I/O NLDD 之射極佈值 4.3 覆蓋式I/O PLDD接點之NPN雙極性電晶體 4.4 水平式矽鍺之PNP雙極性電晶體 4.5 新型垂直雙極性電晶體陣列 4.5.1 P+接點之NPN雙極性電晶體 4.5.2 P+接點陣列 4.6 單接觸點電阻式記憶體 4.6.1 元件結構與製程 4.6.2 特性分析與討論 4.7 小結 第五章 結論 參考文獻

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