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研究生： 劉禮榮
Liu, Li-Jung
論文名稱： 矽鍺、矽/鍺超晶格與鍺通道應用於電荷捕捉式快閃記憶體與金氧半導體元件之電特性研究
Electrical Characteristics of Charge-trapping Flash Memory and MOS Devices with SiGe, Si/Ge Super-lattice and Ge Channels
指導教授： 張廖貴術
Chang Liao, Kuei-Shu
口試委員: 張廖貴術
趙天生
崔秉鉞
蔡銘進
李耀仁
學位類別： 博士
Doctor
系所名稱： 原子科學院 - 工程與系統科學系
Department of Engineering and System Science
論文出版年： 2013
畢業學年度： 101
語文別： 英文
論文頁數： 167
中文關鍵詞： 快閃記憶體 、金氧半導體 、鍺 、矽鍺 、超晶格
外文關鍵詞： Flash memory, MOSFET, Germanium, SiGe, super-lattice
相關次數： 點閱：2  下載：0 
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    • 隨著對非揮發性記憶體與金氧半電晶體元件需求的激增，具有高效能同時保有優良可靠度特性的元件是必要的。並且，為了達到高儲存密度與封裝密度，具有隨縮能力的元件也是必要的。因此，為了改善元件的操作特性與效能，矽鍺通道被視為是最有潛力的ㄧ種提升效能並可降低操作電壓的方式，並且可同時維持元件的微縮能力。在本文中也提供了有關矽鍺通道、高鍺濃度通道與鍺元件之介面層處理的相關文獻回顧。
    在本論文中，矽鍺通道、矽鍺超晶格通道與純鍺通道都應用於提升快閃記憶體元件操作速度的研究上。並且，基於純鍺通道於快閃記憶體上的經驗，我們也對具有不同氧化鍺介面層製程之鍺金氧半元件與金氧半電晶體元件進行研究。
    在使用了矽鍺通道後，快閃記憶體之寫入與抹除速度接獲得顯著的提升，並同時維持了與矽通道元件相同的可靠度特性。我們也同時觀察到，矽鍺通道對於寫入抹除速度的提升，會隨著通道中鍺濃度的增加而上升。因此，為了達到高鍺濃度的通道結構，我們提出了一種新穎的矽/鍺堆疊之超晶格結構。從材料分析的結果我們觀察到，剛堆疊完成之矽/鍺超晶格通道具有極低的表面粗糙度與絕佳的晶格排列，有利於元件的製作。在使用了矽/鍺超晶格之後，快閃記憶體之元件操作速度得到了大幅的提升，並且其特性比使用矽鍺通道之元件更好。同時，使用了矽/鍺超晶格之快閃記憶體元件，可維持與矽通道元件相同的可靠度特性。對於使用了鍺基板之快閃記憶體，與矽通道元件相比，鍺元件具有極快的操作速度，並且可維持甚至提升記憶體之電荷保存能力。然而，鍺快閃記憶體之耐久性較矽通道記憶體元件來的差一些。
    基於製作鍺快閃記憶體元件之經驗，我們也對具有不同氧化鍺介面層製程之鍺金氧半與鍺金氧半電晶體元件進行研究。製作高效能之鍺金氧半與鍺金氧半電晶體元件的關件在於高品質具有化學組成比的超薄氧化鍺介面層。在本研究中，具有低等效氧化層厚度與可接受之閘極漏電流密度之鍺金氧半元件，可利用水氣電漿成長之氧化鍺介面層，搭配同步成長之氮氧化鉿閘極介電層來達成。並且，利用X光光譜儀與高解析度穿透式顯微鏡分析與觀察其水氣電漿成長之氧化鍺介面層，發現此氧化鍺介面層具有+4價氧化態，同時具有0.3 nm 超薄的物理厚度。這是本研究的重要成就。同時，具有高電洞遷移率之鍺金氧半電晶體元件，也可利用此以水氣電漿成長之氧化鍺介面層來達成。為了更進一步的提升氧化鍺介面層的品質，我們也針對不同水氣電漿製程中的成長參數對於鍺金氧半元件電特性的影響進行研究。最後，我們可利用水氣電漿來形成具有高度化學組成比與超薄厚度的氧化鍺介面層的鍺金氧半元件，此鍺金氧半元件具有極低的等效氧化層厚度與高度可靠度特性。

    With the increasing demand on non-volatile memory and MOSFET devices, devices with high performance while maintaining good reliability properties are needed. Also, shrinkage in cell dimension for achieving higher storage and packing density is required. In order to improve the device performance, the utilization of SiGe buried channel is considered most promising for improving performance and lowering the operation voltage, according to the simulations, while stays on the track of device scaling down. Literature reviews on the growth of SiGe buried channel, high-concentration Ge channel and the growth techniques of interfacial layers on Ge substrate are provided.
    In this dissertation, SiGe buried channel, Si/Ge super-lattice channel and Ge channel have been employed for the application on charge-trapping type flash memory devices. Furthermore, Ge MOS and MOSFET devices with different formation processes of GeO2 interfacial layer are also investigated.
    With the employment of SiGe buried channel, both programming / erasing speeds of devices can be improved while maintaining the reliability characteristics as compared with Si-channel devices. Furthermore, the enhancement on device performance increases with the increasing Ge content within channel. Hence, in order to achieve high-Ge content channel structure, we proposed a novel Si/Ge super-lattice channel structure. From the material characterization of the as-deposited super-lattice, the super-lattice structure possesses extremely low surface-roughness and high crystal quality which are helpful for device fabrication. As a result, much better performances of devices with the employment of super-lattice channel are observed as compared to those with SiGe buried channel. At the meanwhile, the reliability properties for devices with employing super-lattice channel are kept which perform as well as Si-channel devices. For flash memory devices on Ge substrate, devices with different interfacial layers are investigated. The device performances are significantly improved by using Ge substrate as compared with Si-channel device and the retention characteristics can be kept simultaneously. However, the endurance property for Ge devices is slightly worse than that of Si-channel device.
    Based on the above experience on fabricating Ge flash memory devices, Ge MOS and MOSFET devices with different formation processes of GeO2 interfacial layer are also investigated in this work. The key challenge of having high performance Ge MOS and MOSFET devices is the formation of high quality stoichiometric GeO2 interfacial layer with ultra-thin thickness. In this work, a low EOT with an acceptable gate leakage current density Ge MOS device can be achieved by using H2O plasma grown GeO2 interfacial layer together with in-situ grown HfON gate dielectric. Furthermore, the oxidation states and thickness of the H2O plasma grown GeO2 interfacial layer are characterized by XPS spectroscopy and HR-TEM, respectively, where the oxidation state is +4 with thickness of around 0.3 nm. It is an important achievement in this work. At the meantime, Ge p-MOSFET devices with high hole mobility are obtained by using the high quality GeO2 interfacial layer grown by H2O plasma process. Furthermore, the effects of various detailed growth-conditions within the H2O plasma process on electrical characteristics of Ge MOS devices are also investigated. A high composition of stoichiometric GeO2 interfacial layer with ultra-thin thickness are achieved which result in ultra-low EOT and high reliability properties of the Ge MOS devices.

    Contents Abstract (in English)……………………………….……………………..…………...……...I Abstract (in Chinese)……………………...……………...……………………...………….III Acknowledgement…………....……………...……..…………………………….……...…...V Contents…………....…………………….…...……..………………………………..…..….VI Table Captions……………...……………...……..…………………………….…………...IX Figure Captions……...…………………….…...……………………………….………........X Chapter 1 Introduction_______________________________________________________________ 1 1.1 General background………………………....………………………………….............1 1.1.1 Charge-trapping type flash memory………………………................................1 1.1.2 The utilization of SiGe buried channel in flash memory…................................4 1.1.3 Growth techniques of SiGe or Ge layer on Si substrate........................……….9 1.1.4 Interfacial layer for Ge devices…………….....................................................16 1.2 Research motivation………………………....…………………………………...........19 1.3 Outline of thesis……………………….... …....…………………………………........20 Chapter 2 Basic Operations and Process Flows of Flash Memory and MOSFET Devices_______ 38 2.1 Basic operations and requirements of flash memory devices…………………............38 2.1.1 FN programming / erasing………………………............................................38 2.1.2 Retention characteristics…...............................................................................39 2.1.3 Endurance characteristics……………..............................................................40 2.1.4 Effective oxide thickness (EOT) and carrier mobility…..................................40 2.2 Process flow for flash memory and MOSFET devices………......................................41 2.2.1 Process flow for charge-trapping flash memory devices..................................42 2.2.2 Process flow for Ge MOS and MOSFET devices.............................................43 Chapter 3 Flash Memory Devices with SiGe Buried Channel______________________________ 46 3.1 Introduction………………………………………………………………..………......46 3.2 Experiments……….......................................................................................................47 3.3 Results and discussion……….......................................................................................48 3.4 Conclusions………........................................................................................................54 Chapter 4 Flash Memory Devices with Si/Ge Super-lattice Channel_________________________ 71 4.1 Introduction…………………........................................................................................71 4.2 Experiments……….......................................................................................................72 4.3 Results and discussion……….......................................................................................74 4.4 Conclusions………........................................................................................................80 Chapter 5 Flash Memory and MOSFET Devices on Ge Substrate__________________________ 92 5.1 Introduction…………………........................................................................................93 5.2 Experiments……….......................................................................................................93 5.3 Results and discussion……….......................................................................................95 5.4 Conclusions………......................................................................................................102 Chapter 6 Ge MOS Devices with Various Growth-conditions within H2O Plasma Process_____ 124 6.1 Introduction…………………......................................................................................124 6.2 Experiments……….....................................................................................................125 6.3 Results and discussion……….....................................................................................125 6.4 Conclusions………......................................................................................................129 Chapter 7 Conclusions and Suggestions_______________________________________________ 149 7.1 Conclusions…………………………………………………...……………………...149 7.2 Suggestions for future work……….............................................................................150 7.2.1 Suggestions for charge-trapping type flash memory devices.........................150 7.2.2 Suggestions for Ge MOS or MOSFET devices..............................................151 References______________________________________________________________ 153 Publication Lists of Li-Jung Liu____________________________________________ 163 Table Captions Table. 1.1 The FN tunneling current and tunneling electric field for devices with different Ge concentrations……………………………………………………………………..22 Table 3.1 Sample conditions for different Ge contents in SiGe channel and various thicknesses of Si-cap…………………………………………………………………………...56 Table 3.2 Split conditions of devices with different Ge content in SiGe buried channel and different Si0.8Ge0.2 thickness in channel…………………………………………...56 Table 4.1 Split conditions of devices with different channel structures………………………82 Table 4.2 Conditions of samples with different stacking structures and thicknesses of Ge top-layer…………………………………………………………………………...82 Table 4.3 Rrms values of the as-deposited super-lattice structures…………………...………..83 Table 4.4 Split conditions of devices with and without Si/Ge super-lattice channel…………83 Table 5.1 Split conditions of Ge flash memory capacitor devices with different interfacial layers……………………………………………………………………………..104 Table 5.2 Split conditions of Ge MOS capacitor devices with different formation processes of the interfacial layers……………………………………………………………...104 Table 5.3 Split conditions of p-channel Ge MOSEFT transistor devices with different formation processes of the interfacial layers……………………………………..105 Table 6.1 Split conditions of the Ge MOS capacitor devices with different desorption time within one cycle treatment of the H2O plasma process…………………………..131 Table 6.2 Split conditions of the Ge MOS capacitor devices with different water-vapor pulse times of the H2O plasma process……………………………………...………….131 Table 6.3 Split conditions of the Ge MOS capacitor devices with different cycles of the plasma treatment within the H2O plasma process……………………….……….132 Figure Captions Fig. 1.1 The schematic cross-section of SONOS-type flash memory device……….………..22 Fig. 1.2 The schematic cross-section of MAHOS-type flash memory device………….…….23 Fig. 1.3 The schematic cross-section of n-channel flash memory devices with SiGe buried channel for simulation under CHISEL operation…………………………………...23 Fig. 1.4 (a) The relation between gate current and the thickness of Si-cap layer. (b) The enhancement of gate current with different Ge content in SiGe buried channel…...24 Fig. 1.5 The erasing speed of devices with different Ge content in SiGe channel…………...24 Fig. 1.6 The schematic cross-section of devices and band structures with SiGe buried channel for simulation…………………………………………………………………….…25 Fig. 1.7 (a) The programming speeds for devices with different content of Ge in SiGe channel. (b) The relation between programming speed and the thickness of Si-cap layer for devices with Si0.6Ge0.4 buried channel……………………………………………...25 Fig. 1.8 The calculated lattice parameter of the germanium layer grown at 330 ℃ from the RHEED pattern……………………………………………………………………..26 Fig. 1.9 The TEM images of the germanium layer grown on the nano-scale Si seeds at (a) low and (b) high magnifications……………………………………………………...…26 Fig. 1.10 The surface morphology of the epitaxial germanium layer on Si substrate (a) before and (b) after H2 annealing at 825 ℃ for 1 hour…………………………………...27 Fig. 1.11 The surface roughness of the epitaxial germanium layer on Si substrate at different H2 annealing temperatures for 1 hour……………………………………………....27 Fig. 1.12 The schematic cross-section of the condensation process. Fig. (a) shows an epitaxial SiGe layer on the SOI substrate. Fig. (b) shows the movement of the germanium atoms within the condensation process. Fig. (c) shows the structure of GOI from the condensed SiGe layer on SOI substrate…………………………………………….28 Fig. 1.13 The TEM image of the pure Ge-layer with high crystal quality on insulator by using condensation technique together with the multi-step oxidation process where the structure is identical to the structure of the germanium on insulator (GOI)………..28 Fig. 1.14 The schematic cross-section of possible path of the threading dislocations within the epitaxial germanium layer. It indicates that the penetration of the threading dislocations would be blocked by the patterned SiO2 gratings……………………..29 Fig. 1.15 The schematic cross-section of the low-temperature germanium layer (a) before and (b) after H2 annealing process………………………………………………………29 Fig. 1.16 The schematic cross-section of the device after 2nd time H2 annealing process……30 Fig. 1.17 The root-mean-square (RMS) surface roughness of the device with difference cycles of growth and H2 annealing processes……………………………………………...30 Fig. 1.18 shows the high resolution TEM image of the Ge layer by using MHAH technique……………………………………………………………………………31 Fig. 1.19 The X-ray rocking curve spectra of the Si (9.8 nm) / Si0.87Ge0.13 (12 nm) for five periods……………………………………………………………………………....31 Fig. 1.20 shows the TEM image of the super-lattice structure and it indicates that there are no obvious dislocations created………………………………………………………..32 Fig. 1.21 The TEM images of the SiGe layer with and without the insertion of Si intermediate layer……………………………………………………………………………...….32 Fig. 1.22 The theoretical critical thickness of an epitaxial Si1-xGex layer on (001) silicon substrate according to the Matthews-Blakeslee theory, and a metastable curve for molecular beam epitaxy (MBE) growth at 550 ℃ is also included…………...…..33 Fig. 1.23 The relation between the germanium oxidation state and the thickness of GeO2 interfacial layer. It shows clearly that the oxidation state decreases with the decreasing thickness of the GeO2 interfacial layer………………………………....33 Fig. 1.24 The relation between the interface trap density and the thickness of GeO2 interfacial layer. It shows clearly that the interface trap density increases with the decreasing thickness of the GeO2 interfacial layer……………………………………………..34 Fig. 1.25 The comparison on band gap characteristics between GeOx and GeO2…………....34 Fig. 1.26 The core-level oxygen 1s HR-XPS spectra of the GeO2/Ge structures with GeO2 IL grown by (i) thermal oxidation and (iii) chemical oxidation processes. It is obvious that the oxygen binding energy of the interfacial layer grown by using thermal oxidation process is higher than that with chemical oxidation……………………..35 Fig. 1.27 The frequency dispersion characteristics of Ge MOS capacitor devices with GeO2 gate oxides, which were fabricated by (a) the high pressure oxidation (HPO) and (b) high pressure oxidation together with low-pressure oxygen annealing (LOA) process………………………………………………………………………………35 Fig. 1.28 The energy dispersion of interface trap density of the Ge MOS capacitor devices with and without LOA process. The minimum value of the interface trap density is about 2*1011 eV-1cm-2 for the device with only HPO process, and the interface trap density can be further reduced down to blow 1011 eV-1cm-2 by using LOA process…………………………………………………………………...………….36 Fig. 1.29 The TEM image of the Ge MOS device with GeO2 interfacial layer grown by using thermal oxidation process. The thickness of the GeO2 interfacial layer is about 11 nm…………………………………………………………………………………...36 Fig. 1.30 The frequency dispersion characteristics of Ge MOS capacitor devices with GeO2 interfacial layer grown by plasma oxidation process. The EOT of the device is 0.76 nm…………………………………………………………………………………...37 Fig. 3.1 Schematic cross-section of flash devices with and without SiGe buried channel…...57 Fig. 3.2 Programming characteristics of flash devices with different Ge contents in SiGe channel……………………………………………………………………………….57 Fig. 3.3 Enhancement on programming time of devices with different Ge contents in SiGe channel……………………………………………………………………………….58 Fig. 3.4 Effective oxide thickness (EOT) of devices with different Ge contents in SiGe channel……………………………………………………………………………….58 Fig. 3.5 Erasing characteristics of flash devices with different Ge contents in SiGe channel..59 Fig. 3.6 Normalized VTH windows for flash device with different Ge contents in SiGe channel under retention tests………………………………………………………………….59 Fig. 3.7 SIMS measurement for concentration profiles of Si and Ge elements……………....60 Fig. 3.8 Programming characteristics of flash devices with SiGe channel and different thicknesses of Si-cap layer…………………………………………………………...60 Fig. 3.9 Effective oxide thickness (EOT) of devices with 11 % Ge content in SiGe channel and different thicknesses of Si-cap layer…………………………………………….61 Fig. 3.10 Enhancement on programming time of devices with 11 % Ge content and different thicknesses of Si-cap layer………………………………………………………..61 Fig. 3.11 Erasing characteristics of flash memory devices with different thicknesses of Si-cap layer……………………………………………………………………………….62 Fig. 3.12 Normalized VTH windows for flash device with different thicknesseses of Si-cap layer under retention tests……………………………………………………..….62 Fig. 3.13 SIMS measurement for the concentration profiles of Hf and Ge elements………...63 Fig. 3.14 (a) The endurance characteristics of SiGe channel device with 11% Ge concentration and 3.5 nm Si cap-layer. (b) The endurance characteristics of control sample (w/o SiGe channel)……………………………………………………………………..63 Fig. 3.15 The programming characteristics of devices with different Ge content in SiGe buried channel under FN operation…………....................................................................64 Fig. 3.16 The erasing characteristics of devices with different Ge content in SiGe buried channel under FN operation………………………………………………………64 Fig. 3.17 Gate current vs. bias voltage of CTF devices with Si and Si0.7Ge0.3 channel for programming operations………………………………………………………….65 Fig. 3.18 Gate current vs. bias voltage of CTF devices with Si and Si0.7Ge0.3 channel for erasing operation………………………………………………………………….65 Fig. 3.19 Retention characteristics of normalized VTH window of CTF devices under room temperature measurement………….......................................................................66 Fig. 3.20 Endurance test up to 106 P/E cycles for CTF devices with Si and Si0.7Ge0.3 channel under FN operation.................................................................................................66 Fig. 3.21 The programming characteristics of devices with different thicknesses of SiGe buried channel under FN operation.........................................................................67 Fig. 3.22 The erasing characteristics of devices with different thicknesses of SiGe buried channel under FN operation....................................................................................67 Fig. 3.23 The programming characteristics of devices with different Ge content in SiGe buried channel under BBHE operation..............................................................................68 Fig. 3.24 The erasing characteristics of devices with different Ge content in SiGe buried channel under FN operation....................................................................................68 Fig. 3.25 The programming characteristics of devices with different thicknesses of SiGe buried channel under BBHE operation...................................................................69 Fig. 3.26 The erasing characteristics of devices with different thicknesses of SiGe buried channel under FN operation....................................................................................69 Fig. 3.27 Retention characteristics of normalized VTH window of CTF devices under room temperature measurement.......................................................................................70 Fig. 3.28 Endurance test up to 106 P/E cycles for CTF devices with Si and Si0.7Ge0.3 channel under BBHE programming and FN erasing............................................................70 Fig. 4.1 (a) HRXRD spectra of SiGe and Si/Ge super-lattice structures (b) Cross-sectional HRTEM image of the as-deposited super-lattice channel. The inset in Fig. 4.1 (a) shows the HR-XRD rocking curve spectra of the SL structures after different thermal treatments……………………………………….......................................84 Fig. 4.2 (a) P/E characteristics of devices with different channel structures at Vg = +/- 17 V. (b) P/E time for VFB shifting 3 V at Vg = +/- 17 V........................................................84 Fig. 4.3 (a) Retention characteristics of normalized VFB windows of devices with different channel structures under room temperature measurement. (b) Endurance test up to 10 K P/E cycles for device with super-lattice channel............................................85 Fig. 4.4 (a) Schematic cross section of flash devices with Si/Ge super-lattice structure in this work. (b) Schematic cross section of super-lattice channel structure.....................85 Fig. 4.5 (a) High resolution X-ray diffraction spectra of different super-lattice structures. (b) HRTEM image of super-lattice structure (Si : 1 nm / Ge : 1.5 nm) .......................86 Fig. 4.6 The relation between VFB shift and gate voltage for devices with and without super-lattice channel (Si : 1 nm / Ge : 1.5 nm) after P/E for 1 sec.........................86 Fig. 4.7 (a) Programming characteristics of flash devices with different stacking structures of super-lattice channel. (b) The enhancement on programming speed for VFB shifting 2.5 V based on Fig. 4(a) .........................................................................................87 Fig. 4.8 (a) Programming characteristics of flash devices with different thicknesses of Ge top-layer in super-lattice channel. (b) The enhancement on programming speed for VFB shifting 2.5 V based on Fig. 5(a) .....................................................................87 Fig.4.9 Erasing characteristics of flash devices with different Si/Ge structures in super-lattice channel....................................................................................................................88 Fig. 4.10 Retention characteristics of normalized VFB windows of devices with different Si/Ge structures in super-lattice channel...........................................................................88 Fig. 4.11 The programming characteristics of devices with and without Si/Ge super-lattice channel under FN operation....................................................................................89 Fig. 4.12 The erasing characteristics of devices with and without Si/Ge super-lattice channel under FN operation.................................................................................................89 Fig. 4.13 The programming characteristics of devices with and without Si/Ge super-lattice channel under BBHE operation..............................................................................90 Fig. 4.14 The erasing characteristics of devices with and without Si/Ge super-lattice channel under BBHE operation............................................................................................90 Fig. 4.15 Endurance test up to 104 P/E cycles for CTF devices with and without super-lattice channel....................................................................................................................91 Fig. 5.1 The programming characteristics of the Ge flash memory capacitor devices with different interfacial layers under FN operation.....................................................105 Fig. 5.2 The programming time for 3 V VFB shift for the Ge flash memory capacitor devices with different interfacial layers under FN operation.............................................106 Fig. 5.3 The erasing characteristics of the Ge flash memory capacitor devices with different interfacial layers under FN operation....................................................................106 Fig. 5.4 The erasing time for 3 V VFB shift for the Ge flash memory capacitor devices with different interfacial layers under FN operation.....................................................107 Fig. 5.5 The values of EOT for the Ge flash memory capacitor devices with different interfacial layers....................................................................................................107 Fig. 5.6 Retention characteristics of normalized VFB window of Ge flash memory capacitor devices under room temperature measurement.....................................................108 Fig. 5.7 Endurance test for the Ge flash memory capacitor devices with different interfacial layers under FN operation.....................................................................................108 Fig. 5.8 The (a) high and (b) low magnification images of the TEM measurement for the Ge flash memory capacitor device with GeO2 interfacial layer..................................109 Fig. 5.9 The core-level Ge 3d HR-XPS spectra of the Al2O3/HfAlO2/Al2O3/GeO2/n-Ge structures with GeO2 interfacial layer...................................................................109 Fig. 5.10 SIMS measurement of the Ge flash memory capacitor device with GeO2 interfacial layer r.....................................................................................................................110 Fig. 5.11 The schematic cross-section of the ALD system used in this work.........................110 Fig. 5.12 The schematic figure of the detailed conditions within one cycle of the plasma process...................................................................................................................111 Fig. 5.13 The CV curves of Ge MOS capacitor devices with different formation processes of GeO2 interfacial layer. The EOT of the device with H2O plasma process is 0.5 nm, which is the lowest one among the three devices..................................................111 Fig. 5.14 The cumulative probability of the EOT values of the devices with different formation processes of interfacial layer................................................................112 Fig. 5.15 The gate leakage current density of the Ge MOS capacitor devices with different formation processes of GeO2 interfacial layer.......................................................112 Fig. 5.16 The cumulative probability of the gate leakage current density of the devices with different formation processes of interfacial layer..................................................113 Fig. 5.17 The relation between EOT and physical thickness of the HfON gate dielectric for the Ge device with GeO2 interfacial layer grown by using H2O plasma process. The dielectric constant of the HfON gate dielectric is about 28..................................113 Fig. 5.18 The gate leakage current density at VG = VFB +1 V versus EOT of n-Ge MOS capacitor devices with some benchmarks for comparison....................................114 Fig. 5.19 The frequency dispersion characteristics for the device with GeO2 interfacial layer grown by O2 plasma process.................................................................................114 Fig. 5.20 The frequency dispersion characteristics for the device with GeO2 interfacial layer grown by H2O plasma process..............................................................................115 Fig. 5.21 The frequency dispersion characteristics for the device with GeO2 interfacial layer grown by H2O2 chemical oxidation process..........................................................115 Fig. 5.22 Hysteresis induced VFB shifts of the Ge MOS capacitor devices with different formation processes of GeO2.................................................................................116 Fig. 5.23 The value of Dit at mid-gap for devices with different formation processes of GeO2 interfacial layer......................................................................................................116 Fig. 5.24 Stress induced VFB shifts under 3.3 MV/cm, which indicates good quality and reliability property of HfON gate dielectrics deposited on plasma grown GeO2 interfacial layers....................................................................................................117 Fig. 5.25 Stress induced leakage currents under 3.3 MV/cm, which indicates excellent interface quality and reliability property of plasma grown GeO2 interfacial layer.......................................................................................................................117 Fig. 5.26 The (a) high and (b) low magnification images of the TEM for the Ge MOS device with H2O plasma process......................................................................................118 Fig. 5.27 The (a) high and (b) low magnification images of the TEM for the Ge MOS device with H2O2 chemical oxidation process..................................................................118 Fig. 5.28 The HR-XRD spectra of devices with GeO2 interfacial layer grown by O2 and H2O plasma processes, which indicates tetragonal phase HfON layers........................119 Fig. 5.29 The HR-XRD spectrum of device with GeO2 interfacial layer grown by H2O2 chemical oxidation, which indicates monoclinic phase HfON layer....................119 Fig. 5.30 (a) The Ge 3d spectrum of XPS measurement for Ge MOS capacitor device with GeO2 interfacial layer grown by O2 plasma process...................................................................................................................120 Fig. 5.30 (b) The Ge 3d spectrum of XPS measurement for Ge MOS capacitor device with GeO2 interfacial layer grown by H2O plasma process...................................................................................................................120 Fig. 5.30 (c) The Ge 3d spectrum of XPS measurement for Ge MOS capacitor device with GeO2 interfacial layer grown by H2O2 chemical oxidation process...................................................................................................................121 Fig. 5.31 The process flow and schematic cross-section of the p-channel Ge MOSEFT transistor devices where the GeO2 interfacial layers are fabricated by three different formation processes................................................................................121 Fig. 5.32 The Id-Vg characteristics of the p-channel Ge MOSFET transistor devices with different formation processes of GeO2 interfacial layer........................................122 Fig. 5.33 Hole mobility as a function of the Ns for the p-channel Ge MOSFET transistor devices with different formation processes of GeO2 interfacial layer...................122 Fig. 5.34 The peak hole mobility of p-channel Ge (100) MOSFET in this work, compared with the recently reported results..........................................................................123 Fig. 6.1 The CV curves of Ge MOS capacitor devices with 10 sec desorption time within one cycle treatment of the H2O plasma process..........................................................132 Fig. 6.2 The CV curves of Ge MOS capacitor devices with 30 sec desorption time within one cycle treatment of the H2O plasma process..........................................................133 Fig. 6.3 The CV curves of Ge MOS capacitor devices with 60 sec desorption time within one cycle treatment of the H2O plasma process..........................................................133 Fig. 6.4 The cumulative probability of the gate leakage current density of the Ge MOS capacitor devices with different desorption time within one cycle treatment of the H2O plasma process..............................................................................................134 Fig. 6.5 The gate leakage current density at VG = VFB +1 V versus EOT of n-Ge MOS capacitor devices with some benchmarks for comparison....................................134 Fig. 6.6 The gate leakage current density at VG = VFB +1 V versus EOT of n-Ge MOS capacitor devices with different desorption time within one cycle treatment of the H2O plasma process..............................................................................................135 Fig. 6.7 The Ge 3d spectrum of XPS measurement for the device with 10 sec desorption time within one cycle treatment of the H2O plasma process........................................135 Fig. 6.8 The Ge 3d spectrum of XPS measurement for the device with 60 sec desorption time within one cycle treatment of the H2O plasma process........................................136 Fig. 6.9 The CV curves of Ge MOS capacitor devices with 0.16 sec water-vapor pulse time of the H2O plasma process........................................................................................136 Fig. 6.10 The CV curves of Ge MOS capacitor devices with 0.24 sec water-vapor pulse time of the H2O plasma process....................................................................................137 Fig. 6.11 The CV curves of Ge MOS capacitor devices with 0.32 sec water-vapor pulse time of the H2O plasma process....................................................................................137 Fig. 6.12 The cumulative probability of the gate leakage current density of the Ge MOS capacitor devices with different water-vapor pulse times of the H2O plasma process...................................................................................................................138 Fig. 6.13 The gate leakage current density at VG = VFB +1 V versus EOT of n-Ge MOS capacitor devices with some benchmarks for comparison....................................138 Fig. 6.14 The gate leakage current density at VG = VFB +1 V versus EOT of n-Ge MOS capacitor devices with different water-vapor pulse times of the H2O plasma process...................................................................................................................139 Fig. 6.15 Hysteresis induced VFB shifts of the Ge MOS capacitor devices with different water-vapor pulse times of the H2O plasma process.............................................139 Fig. 6.16 Stress induced VFB shifts under 1.7 MV/cm, which indicates the quality and reliability property of HfON gate dielectrics can be improved by increasing the water-vapor pulse times of the H2O plasma process.............................................140 Fig. 6.17 Stress induced leakage currents under 1.7 MV/cm, which indicates the interface quality and reliability property of GeO2 interfacial layer can be improved by increasing the water-vapor pulse times of the H2O plasma process.....................140 Fig. 6.18 The Ge 3d spectrum of XPS measurement for the device with original water-vapor pulse time of the H2O plasma process..................................................................141 Fig. 6.19 The Ge 3d spectrum of XPS measurement for the device with 0.16 sec water-vapor pulse time of the H2O plasma process..................................................................141 Fig. 6.20 The Ge 3d spectrum of XPS measurement for the device with 0.24 water-vapor pulse time of the H2O plasma process..................................................................142 Fig. 6.21 The CV curves of Ge MOS capacitor devices with 50 cycles of the plasma treatment within the H2O plasma process.............................................................................142 Fig. 6.22 The CV curves of Ge MOS capacitor devices with 100 cycles of the plasma treatment within the H2O plasma process.............................................................143 Fig. 6.23 The CV curves of Ge MOS capacitor devices with 150 cycles of the plasma treatment within the H2O plasma process.............................................................143 Fig. 6.24 The cumulative probability of the gate leakage current density of the Ge MOS capacitor devices with different cycles of plasma treatment within the H2O plasma process...................................................................................................................144 Fig. 6.25 The gate leakage current density at VG = VFB +1 V versus EOT of n-Ge MOS capacitor devices with some benchmarks for comparison....................................144 Fig. 6.26 The gate leakage current density at VG = VFB +1 V versus EOT of n-Ge MOS capacitor devices with different cycles of plasma treatment within the H2O plasma process...................................................................................................................145 Fig. 6.27 Hysteresis induced VFB shifts of the Ge MOS capacitor devices with different cycles of plasma treatment within the H2O plasma process............................................145 Fig. 6.28 Stress induced VFB shifts under 1.7 MV/cm, which indicates the quality and reliability property of HfON gate dielectrics can be improved by increasing the cycle number of plasma treatment within the H2O plasma process……..............146 Fig. 6.29 Stress induced leakage currents under 1.7 MV/cm, which indicates the interface quality and reliability property of GeO2 interfacial layer can be improved by increasing the cycle number of plasma treatment within the H2O plasma process…………………………………………………………………………...146 Fig. 6.30 The Ge 3d spectrum of XPS measurement for the device with 50 cycles of the plasma treatment within the H2O plasma process.................................................147 Fig. 6.31 The Ge 3d spectrum of XPS measurement for the device with 100 cycles of the plasma treatment within the H2O plasma process.................................................147 Fig. 6.32 The Ge 3d spectrum of XPS measurement for the device with 150 cycles of the plasma treatment within the H2O plasma process.................................................148

    [1] The International Technology Roadmap for Semiconductors (ITRS), 2012.
    [2] Srikant Jayanti, Xiangyu Yang, Rahul Suri, and Veena Misra, “Ultimate Scalability of TaN Metal Floating Gate with Incorporation of High-K Blocking Dielectrics for Flash Memory Applications,” in IEDM Tech. Dig., pp. 106-109, 2010
    [3] C. Y. Tsai, T. H. Lee, Albert Chin, Hong Wang, C. H. Cheng, and F. S. Yeh, “Highly-Scaled 3.6-nm ENT Trapping Layer MONOS Device with Good Retention and Endurance”, in IEDM Tech. Dig., pp. 110-113, 2010.
    [4] C. H. Lai, Albert Chin, H. L. Kao, K. M. Chen, M. Hong, J. Kwo, C. C. Chi, “Very Low Voltage SiO2/HfON/HfAlO/TaN Memory with Fast Speed and Good Retention”, in VLSI Symp. Tech. Dig., pp. 44-45, 2006.
    [5] Chang Hyun Lee, Kyung In Choi, Myoung Kwan Cho, Yun Heub Song, Kyu Charn Park, and Kinam Kim, “A Novel SONOS Structure of SiO2/SiN/Al2O3 with TaN metal gate for multi-giga bit flash memories,” in IEDM Tech. Dig., pp. 613-616, 2003.
    [6] Xuguang Wang, Jun Liu, Weiping Bai, and Dim-Lee Kwong, “A Novel MONOS-Type Nonvolatile Memory Using High-κ Dielectrics for Improved Data Retention and Programming Speed,” IEEE Trans. Electron Devices, vol. 51, no. 4, pp. 597-602, Apr. 2004.
    [7] Ping-Hung Tsai, Kuei-Shu Chang-Liao, Te-Chiang Liu, Tien-Ko Wang, Pei-Jer Tzeng, Cha-Hsin Lin, L. S. Lee, and Ming-Jinn Tsai, “Charge-trapping-type flash memory device with stacked high-κ charge-trapping layer,” IEEE Electron Device Lett., vol. 30, no. 7, pp.775-777, July. 2009.
    [8] Chang Yong Kang, “Barrier engineering in metal-aluminum oxide-nitride-oxide-silicon (MANOS) flash memory: Invited,” Curr. Appl. Phys., vol. 10, pp. e27-e31, Sept. 2010.
    [9] T. Sugizaki, M. Kohayashi, M. Ishidao, H. Minakata, M. Yamaguchi, Y. Tamura, Y. Sugiyama, T. Nakanishi, and H. Tanaka, “Novel Multi-bit SONOS Type Flash Memory Using a Highk Charge Trapping Layer,” in VLSI Symp. Tech. Dig., pp. 27-28, 2003.
    [10] Hsiang-Yueh Lai, Kuei-Shu Chang-Liao, Tien-Ko Wang, Ping-Kun Wang, Chin-Lung Cheng, “Performance improvement of flash memories with HfOxNy/SiO2 stack tunnel dielectrics”, J. Vac. Sci. Technol. B., vol. 24, pp. 1683-1688, 2006.
    [11] L. M. Weltzer, and S. K. Banerjee, “Enhanced CHISEL Programming in Flash Memory Devices with SiGe Buried Layer,” Proc. Non-Volatile Memory Technol. Symp., pp. 31-33, 2004.
    [12] D. L. Kencke, Xin Wang, Q. Ouyang, S. Mudanai, A. Tasch, Jr., and S. K. Banerjee, “Enhanced secondary electron injection in novel SiGe flash memory devices,” in IEDM Tech. Dig., pp. 105-108, 2000.
    [13] Scott C. Wolfson, and Fat Duen Ho, “Transient simulation to analyze flash memory erase improvements due to germanium content in the substrate,” IEEE Trans. Electron Devices, vol. 57, no. 10, pp. 2499-2503, Oct. 2010.
    [14] Chi-Chao Wang, Kuei-Shu Chang-Liao, Chun-Yuan Lu, and Tien-Ko Wang, “Enhanced band-to-band-tunneling-induced hot-electron injection in p-channel flash by band-gap offset modification,” IEEE Electron Device Lett., vol. 27, no. 9, pp. 749-751, Sept. 2006.
    [15] Li-Jung Liu, Kuei-Shu Chang-Liao, Wen-Chun Keng, and Tien-Ko Wang, “Improvement on programming and erasing speeds for charge-trapping flash memory device with SiGe buried channel,” Solid State Electron., vol. 54, pp. 1113-1118, 2010.
    [16] Li-Jung Liu, Kuei-Shu Chang-Liao, Yi-Chuen Jian, Jen-Wei Cheng, and Tien-Ko Wang, “Enhanced programming and erasing speeds in p-channel charge-trapping flash memory device with SiGe buried channel,” IEEE Electron Device Lett., vol. 33, no. 9, pp. 1264-1266, Sept. 2012.
    [17] Scott C. Wolfson, and Fat Duen Ho, “Transient simulation to analyze flash memory programming improvements due to germanium content in the substrate using nonquasi-static techniques,” Microelectron. Eng., vol. 99, pp. 23-27, Jun. 2012.
    [18] Jungwoo Oh, Prashant Majhi, Hideok Lee, Oooksang Yoo, Sanjay Banerjee, Chang Yong Kang, Ji-Woon Yang, Rusty Harris, Hsing-Huang Tseng, and Raj Jammy, “Improved Electrical Characteristics of Ge-on-Si Field-Effect Transistors With Controlled Ge Epitaxial Layer Thickness on Si Substrates,” IEEE Electron Device Lett., vol. 28, no. 11, pp. 1044-1046, Nov. 2007.
    [19] Yu-Hsien Lin, Chao-Hsin Chien, Chun-Yen Chang and Tan-Fu Lei, “Annealing temperature effect on the performance of nonvolatile HfO2 Si-oxide-nitride-oxide-silicon-type flash memory”, J. Vac. Sci. Technol., Vol. 24„No.3, pp. 682-685, 2006
    [20] Rui Zhang, Takashi Iwasaki, Noriyuki Taoka, Mitsuru Takenaka, and Shinichi Takagi, “High-Mobility Ge pMOSFET With 1-nm EOT Al2O3/GeOx/Ge Gate Stack Fabricated by Plasma Post Oxidation”, IEEE Trans. Electron Devices, vol. 59, no. 2, pp. 335-341, Feb. 2012.
    [21] Takahiro Ohnakado, Hiroshi Onoda, Osamu Sakamoto, Kiyoshi Hayashi, Naho Nishioka, Hiroshi Takada, Kazuyuki Sugahara, Natsuo Ajika, and Shin-ichi Satoh, “Device Characteristics of 0.35 m P-Channel DINOR Flash Memory Using Band-to-Band Tunneling-Induced Hot Electron (BBHE) Programming”, IEEE Trans. Electron Devices, vol. 46, no. 9, pp. 1866-1871, Sep. 1999.
    [22] B. Van Zeghbroeck, Principles of Semiconductor Devices. Boulder, CO: Univ. Colorado, 2007.
    [23] Kuo-Nan Yang, Huan-Tsung Huang, Ming-Chin Chang, Che-Min Chu, Yuh-Shu Chen, Ming-Jer Chen, Yeou-Ming Lin, Mo-Chiun Yu, Simon M. Jang, Douglas C. H. Yu, and M. S. Liang, “A physical model for hole direct tunneling current in P+ poly-gate PMOSFETs with ultrathin gate oxides,” IEEE Trans. Electron Devices, vol. 47, no. 11, pp. 2161-2166, Nov. 2000.
    [24] C.-H Lin, B.-C Hsu, M. H. Lee, and C. W. Liu, “A Comprehensive Study of Inversion Current in MOS Tunneling Diodes,” IEEE Trans. Electron Devices, vol. 48, no. 9, pp. 2125-2130, Sept. 2001.
    [25] J. W. Matthews, and A. E. Blakeslee, “Defects in epitaxial multilayers,” J. Cryst. Growth., vol. 32, pp. 265-273, June. 1975.
    [26] Douglas J Paul, “Si/SiGe heterostructures: from material and physics to devices and circuits,” Semicond. Sci. Technol., vol. 19, pp. R75-R108, Sept. 2004.
    [27] Rui Zhang, Po-Chin Huang, Ju-Chin Lin, Noriyuki Taoka, Mitsuru Takenaka, and Shinichi Takagi, “High-Mobility Ge p- and n-MOSFETs With 0.7-nm EOT Using HfO2/Al2O3/GeOx/Ge Gate Stacks Fabricated by Plasma Postoxidation”, IEEE Trans. Electron Devices, vol. 60, no. 3, pp. 927-934, Mar. 2013.
    [28] M. Halbwax, D. Bouchier, V. Yam, D. Débarre, and Lam H. Nguyen, Y. Zheng, P. Rosner, M. Benamara, and H. P. Strunk, and C. Clerc, “Kinetics of Ge growth at low temperature on Si.001. by ultrahigh vacuum chemical vapor deposition”, J. Apl. Phys., vol. 97, 064907, 2005.
    [29] M. T. Currie, S. B. Samavedam, T. A. Langdo, C. W. Leitz, and E. A. Fitzgerald, “Controlling threading dislocation densities in Ge on Si using graded SiGe layers and chemical-mechanical polishing”, Appl. Phys. Lett., vol. 72, no. 14, pp. 1718-1720, 1998.
    [30] C. Renard, M. Halbwax, D. Cammilleri, F. Fossard, V. Yam, D. Bouchier, and Y. Zheng, “Ge growth over thin SiO2 by UHV–CVD for MOSFET applications”, Thin Solid Films., vol. 517, pp. 401-403, 2008.
    [31] Ammar Nayfeh, Chi On Chui, Krishna C. Saraswat, and Takao Yonehara, “Effects of hydrogen annealing on heteroepitaxial-Ge layers on Si: Surface roughness and electrical quality”, Appl. Phys. Lett., vol. 85, no. 14, pp. 2815-2817, 2004.
    [32] Nobuhiko Sato and Takao Yonehara, “Hydrogen annealed silicon-on-insulator”, Appl. Phys. Lett., vol. 65, no. 15, pp. 1924-1926, 1994.
    [33] S. Horch, H. T. Lorensen, S. Helveg, E. Lngsgaard, I. Stensgaard, K. W. Jacobsen, J. K. Norskov and F. Besenbacher, “Enhancement of surface self-diffusion of platinum atoms by adsorbed hydrogen”, Nature, vol. 398, no. 11, pp. 134-136, 1994.
    [34] Shu Nakaharai, Tsutomu Tezuka, Naoharu Sugiyama, Yoshihiko Moriyama, and Shin-ichi Takagi, “Characterization of 7-nm-thick strained Ge-on-insulator layer fabricated by Ge-condensation technique”, Appl. Phys. Lett., vol. 83, no. 17, pp. 3516-3518, 2003.
    [35] S. Balakumar, G. Q. Lo, C. H. Tung, R. Kumar, N. Balasubramanian, D. L. Kwong, C. S. Ong and M. F. Li, “SiGe amorphization during Ge condensation in silicon germanium on insulator”, Appl. Phys. Lett., vol. 89, 042115, 2006.
    [36] J. Lee, K.L. Wang, H.-T. Chen, and L.-J. Chen, “High-quality heteroepitaxial Ge growth on nano-patterned Si templates using diblock copolymer patterning”, J. Crystal Growth, vol. 89, 042115, 2006.
    [37] Hyun-Yong Yu, Masaharu Kobayashi, Woo Shik Jung, Ali K. Okyay, Yoshio Nishi, Krishna C. Saraswat, “High Performance n-MOSFETs with Novel Source/Drain on Selectively Grown Ge on Si for Monolithic Integration,” in IEDM Tech. Dig., pp. 685-688, 2009.
    [38] S.R. Sheng, M. Dion, S.P. McAlister, N.L. Rowell, “Growth and characterization of Si/SiGe strained-layer superlattices on bulk single-crystal SiGe and Si substrates”, J. Crystal Growth, vol. 253, pp. 77-84, 2003.
    [39] LIANG Renrong, WANG Jing, and XU Jun, “Fabrication of High Quality SiGe Virtual Substrates by Combining Misfit Strain and Point Defect Techniques”, Tsinghua Sci. Technol., vol. 14, no. 1, pp. 62-67, 2009.
    [40] P S Chen, S W Lee, M H Lee and C W Liu, “Growth of high-quality relaxed SiGe films with an intermediate Si layer for strained Si n-MOSFETs”, Semicond. Sci. Technol., vol. 21, pp. 479-485, 2006.
    [41] Chia Ching Yeo, Byung Jin Cho, F. Gao, S. J. Lee, M. H. Lee, C.-Y. Yu, C. W. Liu, L. J. Tang, and T. W. Lee, “Electron Mobility Enhancement Using Ultrathin Pure Ge on Si Substrate,” IEEE Electron Device Lett., vol. 26, no. 10, pp. 761-763, Sept. 2005.
    [42] S C Jain and W Hayes, “Structure, properties and applications of GexSi1-x strained layers and superlattices”, Semicond. Sci. Technol., vol. 6, pp. 547-576, 1991.
    [43] R. Hull, J. C. Bean, F. Cerdeira, A. T. Fiory, and J. M. Gibson, “Stability of semiconductor strainedlayer superlattices,” Appl. Phys. Lett., vol. 48, no. 56, pp. 56-58, 1986.
    [44] Pairot Moontragoon, Zoran Ikonic, and Paul Harrison, “Band Structure Calculations of Si-Ge-Sn Alloys: Achieving direct band gap materials”, Semicond. Sci. Technol., vol. 22, pp. 742-748, 2007.
    [45] Liqing Wu, Meichun Huang, Zizhong Zhu, and Kaihang Li, “Band gap and heterojunction discontinuities of pseudomorphic Si1-x-yGexCy alloy layers on Si(001),” J. Appl. Phys., vol. 84, no. 4, pp. 2165-2169, 1998.
    [46] P. Zimmerman, G. Nicholas, B. De-Jaeger, B. Kaczer, A. Stesmans, L.-A. Ragnarsson, D. P. Brunco, F. E. Leys, M. Caymax, G. Winderickx, K. Opsomer, M. Meuris, and M. M. Heyns, “High performance Ge pMOS devices using a Si-compatible process flow,” in IEDM Tech. Dig., pp. 1-4, 2006.
    [47] H. Shang, M. M. Frank, E. P. Gusev, J. O. Chu, S. W. Bedell, K. W. Guarini, and M. Ieong, “Germanium channel MOSFETs: opportunities and challenges,” IBM J. Res. & Dev., vol. 50, no. 4/5, pp. 377-386, Sep. 2006.
    [48] R. Zhang, T. Iwasaki, N. Taoka, M. Takenaka, and S. Takagi, “Al2O3/GeOx/Ge gate stacks with low interface trap density fabricated by electron cyclotron resonance plasma postoxidation,” Appl. Phys. Lett., vol. 98, no. 11, p. 112902, Mar. 2011.
    [49] Florence Bellenger, Brice De Jaeger, Clement Merckling, Michel Houssa, Julien Penaud, Laura Nyns, Evi Vrancken, Matty Caymax, Marc Meuris, Thomas Hoffmann, Kristin De Meyer, and Marc Heyns, “High FET performance for a future CMOS GeO2-based technology,” IEEE Electron Device Lett., vol. 31, no. 5, pp. 402-404, May. 2010.
    [50] F. Ji, J. P. Xu, P. T. Lai, C. X. Li, and J. G. Liu, “Improved interfacial properties of Ge MOS capacitor with high-κ dielectric by using TaON/GeON dual interlayer,” IEEE Electron Device Lett., vol. 32, no. 2, pp. 122-124, Feb. 2011.
    [51] Choong Hyun Lee, Tomonori Nishimura, Kosuke Nagashio, Koji Kita, and Akira Toriumi, “High-electron-mobility Ge/GeO2 n-MOSFETs with two-step oxidation,” IEEE Trans. Electron Devices, vol. 58, no. 5, pp. 1295-1301, May. 2011.
    [52] Duygu Kuzum, Tejas Krishnamohan, Abhijit J. Pethe, Ali K. Okyay, Yasuhiro Oshima, Yun Sun, James P. McVittie, Piero A. Pianetta, Paul C. McIntyre, and Krishna C. Saraswat, “Ge-interface engineering with ozone oxidation for low interface-state density,” IEEE Electron Device Lett., vol. 29, no. 4, pp. 328-330, Apr. 2008.
    [53] Chi On Chui, Fumitoshi Ito, and Krishna C. Saraswat, “Nanoscale germanium MOS dielectrics-Part I: germanium oxynitrides,” IEEE Trans. Electron Devices, vol. 53, no. 7, pp. 1501-1508, Jul. 2006.
    [54] Huiling Shang, Kam-Leung Lee, P. Kozlowski, C. D’Emic, I. Babich, E. Sikorski, Meikei Ieong, H.-S. P. Wong, Kathryn Guarini, and W. Haensch, “Self-aligned n-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric and tungsten gate,” IEEE Electron Device Lett., vol. 25, no. 3, pp. 135-137, Mar. 2004.
    [55] Katsuhiro Kutsuki, Gaku Okamoto, Takuji Hosoi, Takayoshi Shimura, and Heiji Watanabe, “Humidity-dependent stability of amorphous germanium nitrides fabricated by plasma nitridation,” Appl. Phys. Lett., vol. 91, no. 16, p. 163501, Oct. 2007.
    [56] Ruilong Xie, and Chunxiang Zhu, “Effects of sulfur passivation on germanium MOS capacitors with HfON gate dielectric,” IEEE Electron Device Lett., vol. 28, no. 11, pp. 976-979, Nov. 2007.
    [57] L. Lin, K. Xiong, and J. Robertson, “Atomic structure, electronic structure, and band offsets at Ge:GeO:GeO2 interfaces,” Appl. Phys. Lett., vol. 97, 242902, 2010.
    [58] C. H. Lee, T. Nishimura, N. Saido, K. Nagashio, K. Kita and A. Toriumi, “Record-high Electron Mobility in Ge n-MOSFETs exceeding Si Universality,” in IEDM Tech. Dig., pp. 457-460, 2009.
    [59] Yen-Chun Fu, William Hsu, Yen-Ting Chen, Huang-Siang Lan, Cheng-Han Lee, Hung-Chih Chang, Hou-Yun Lee, Guang-Li Luo, Chao-Hsin Chien, C. W. Liu, Chenming Hu, and Fu-Liang Yang, “High mobility high on/off ratio C-V dispersion-free Ge n-MOSFETs and their strain response,” in IEDM Tech. Dig., pp. 432-435, 2010.
    [60] R. Zhang, P. C. Huang, N. Taoka, M. Takenaka and S. Takagi, “Novel Multi-bit SONOS Type Flash Memory Using a Highk Charge Trapping Layer,” in VLSI Symp. Tech. Dig., pp. 161-162, 2012.
    [61] T. Mikolajick, M. Specht. N.Nage, T.Mueller, S. Riedel, F. Beug, T.Melde and K.-H. Kuisters, “The Future of Charge Trapping Memories”, in VLSI Tech. System and Application, pp. 23-25, 2007.
    [62] Chang-Hyun Lee, Jungdal Choi, Changseok Kang, Yoocheol Shin, Jang-Sik Lee, Jongsun Sel, Jaesung Sim, Sanghun Jeon, Byeong-In Choe, Dukwon Bae, Kitae Park, and Kinam Kim, “Multi-Level NAND Flash Memory with 63 nm-node TANOS (Si-Oxide-SiN-Al2O3-TaN) Cell Structure,” in VLSI Symp. Tech. Dig., pp. 21-22, 2006.
    [63] Shaw-Hung Gu, Chih-Wei Hsu, Tahui Wang, Wen-Pin Lu, Yen-Hui Joseph Ku, and Chih-Yuan Lu, “Numerical Simulation of Bottom Oxide Thickness Effect on Charge Retention in SONOS Flash Memory Cells,” IEEE Trans. Electron Devices, vol. 54, no. 1, pp. 90-97, Apr. 2007.
    [64] D. C. Gilmer, N. Goel, H. Park, C. Park, S. Verma ,G. Bersuker, P. Lysaght, H.-H. Tseng, P. D. Kirsch, K. C. Saraswat and R. Jammy, “Engineering the Complete MANOS-type NVM Stack for Best in Class Retention Performance”, in IEDM Tech. Dig., pp. 439-442, 2009.
    [65] H. Park, G. Bersuker, M. Jo, D. Veksler, K. Y. Lim, D. Gilmer, N. Goel, C. Y. Kang, C. Young, M. Chang, H. Hwang, H-H. Tseng, P. D. Kirsch, R. Jammy, “Tunnel Oxide Degradation in TANOS Devices and its Origin”, in VLSI Tech. System and Application, pp. 50-51, 2010.
    [66] Jermyn M. Z. Tseng, Bradley J. Larsen, Yang Xiao, and Donald A. Erickson, “A Novel Method to Separately Investigate Program and Erase Degradation Mechanisms in Flash Memory Cells,” IEEE Trans. Electron Devices, vol. 48, no. 12, pp. 2947-2951, Dec. 2001.
    [67] Antonio Arreghini, Francesco Driussi, Elisa Vianello, David Esseni, Michiel J. van Duuren, Dusan S. Golubovic, Nader Akil, and Rob van Schaijk, “Experimental characterization of the vertical position of the trapped charge in Si nitride-based nonvolatile memory cells,” IEEE Trans. Electron Devices, vol. 55, no. 5, pp. 1211-1219, May. 2008.
    [68] Sheng-Chih Lai, Hang-Ting Lue, Chien-Wei Liao, Yu-Fong Huang, Ming-Jui Yang, Yi-Hsien Lue, Tai-Bor Wu, Jung-Yu Hsieh, Szu-Yu Wang, Shih-Ping Hong, Fang-Hao Hsu, Chih-Yen Shen, Guang-Li Luo, Chao-Hsin Chien, Kuang-Yeu Hsieh, Rich Liu, and Chih-Yuan Lu, “An oxide-buffered BE-MANOS charge-trapping device and the role of Al2O3,” in Proc. IEEE Nonvolatile Semicond. Memory Workshop, 2008, pp. 101-102.
    [69] Gang Zhang, Xin-Peng Wang, Won-Jong Yoo, and Ming-Fu Li, “Spatial Distribution of Charge Traps in a SONOS-Type Flash Memory Using a High-κ Trapping Layer,” IEEE Trans. Electron Devices, vol. 54, no. 12, pp. 3317-3324, Dec. 2007.
    [70] Gang Zhang, Won-Jong Yoo, and Chung-Ho Ling, “Hot-Electron Capture for CHEI Programming in SONOS-Type Flash Memory Using High-κ Trapping Layer,” IEEE Trans. Electron Devices, vol. 55, no. 6, pp. 1502-1510, Jun. 2008.
    [71] Young-Joo Song, Jung-Wook Lim, Sang-Hoon Kim, Hyun-Chul Bae, Jin-Young Kang, Kyung-Wan Park, Kyu-Hwan Shim, “Effects of Si-cap layer thinning and Ge segregation on the characteristics of Si/SiGe/Si heterostructure pMOSFETs,” Solid State Electronics, vol. 46, pp. 1983-1989, 2002.
    [72] M. Spadafora, G. Privitera, A. Terrasi, S. Scalese, C. Bongiorno, A. Carnera, M. Di Marino, and E. Napolitani, “Oxidation rate enhancement of SiGe epitaxial films oxidized in dry ambient”, Appl. Phys. Lett., vol. 83, no. 18, pp. 3713-3715, 2003.
    [73] M. Fatemi and R. E. Stahlbush, “X‐ray rocking curve measurement of composition and strain in Si‐Ge buffer layers grown on Si substratest”, Appl. Phys. Lett., vol. 58, no. 8, pp. 825-827, 1990.
    [74] L. Larcher, P. Pavan, and B. Eitan, “On the physical mechanism of the NROM memory erase,” IEEE Trans. Electron Devices, vol. 51, no. 10, pp. 1593-1599, Oct. 2004.
    [75] Chih-Hao Chen, Kai-Chieh Chuang, and Jenn-Gwo Hwu, “Characterization of Inversion Tunneling Current Saturation Behavior for MOS(p) Capacitors With Ultrathin Oxides and High-k Dielectrics,” IEEE Trans. Electron Devices, vol. 56, no. 6, pp. 1262-1268, Jun. 2009.
    [76] Po-Tsun Liu, Chen-Shuo Huang, Yi-Ling Huang, Jing-Ru Lin, Szu-Lin Cheng, Yoshio Nishi, and S. M. Sze, “Effects of postgate dielectric treatment on germanium-based metal-oxide-semiconductor device by supercritical fluid technology,” Appl. Phys. Lett., vol. 96, no. 11, p. 112902, Mar. 2010.
    [77] Hiroshi Matsubara, Takashi Sasada, Mitsuru Takenaka, and Shinichi Takagi, “Evidence of low interface trap density in GeO2/Ge metal-oxide-semiconductor structures fabricated by thermal oxidation,” Appl. Phys. Lett., vol. 93, no. 3, p. 032104, Jul. 2008.
    [78] Ruilong Xie, Thanh Hoa Phung, Wei He, Mingbin Yu, and Chunxiang Zhu, “Interface-engineered high-mobility high-k/Ge pMOSFETs with 1-nm equivalent oxide thickness,” IEEE Trans. Electron Devices, vol. 56, no. 6, pp. 1330–1337, Jun. 2009.
    [79] K. Prabhakaran, F. Maeda, Y. Watanabe, and T. Ogino, “Distinctly different thermal decomposition pathways of ultrathin oxide layer on Ge and Si surfaces,” Appl. Phys. Lett., vol. 76, no. 16, pp. 2244-2246, Feb. 2000.
    [80] M.-H. Cho, Y. S. Roh, C. N. Whang, K. Jeong, S. W. Nahm, D.-H. Ko, J. H. Lee, N. I. Lee, and K. Fujihara, “Thermal stability and structural characteristics of HfO2 films on Si 100 grown by atomic-layer deposition,” Appl. Phys. Lett., vol. 81, no. 3, p. 032104, Jul. 2002.
    [81] Weiping Bai, Nan Lu, Andrew P. Ritenour, Minjoo Larry Lee, Dimitri A. Antoniadis, and Dim-Lee Kwong, “The Electrical Properties of HfO2 Dielectric on Germanium and the Substrate Doping Effect,” IEEE Trans. Electron Devices, vol. 53, no. 10, pp. 2551–2558, Oct. 2006.

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