我們提出了一個電路名為「具有溫度追蹤功能的寬調控區間可編程式相位偏移器」。此電路分為校正區、粗調區與微調區三個區間，並使用校正、粗調、微調與正常操作四個步驟產生最後的相位偏移。此電路具有細胞化的特性，這使得它可以很輕易地被轉移到下一世代的製程，它不只具有產生可指定且可控制的相位偏移量，並具有非常寬的調控區間，其產生的相位偏移量可介於0ns到100ns。一般而言，溫度將會帶給這種時序控制電路很大的影響，在沒有作溫度追蹤功能的電路中，當溫度改變愈多，相位偏移量愈大。為了達到溫度追蹤功能，此論文在子電路中提出一通用性的鎖延遲回路，與傳統的鎖延遲回路不同，其在時間數位轉器作為回授的幫助下偵測延遲線兩端，使得電路不再操作在開路之下得以追蹤溫度。根據Nanosim模擬結果，在TT角落之下，從25度C升高到125度C時，在沒有溫度追蹤功能的情況下會有96ps的相位誤差，而加入溫度追蹤功能時，可將溫度改變期間的相位誤差壓至-7至12ps。最後，同樣在TT角落並採用Nanosim模擬之下，經由10,000個控制碼中模擬了400個控制碼，此電路產生了38ps-100,036ps的相位偏移量，雖然其具有38ps的offset error，但經由線性分析確定其結果是不差的。

This thesis presents a circuit named wide tuning range programmable phase shifter with temperature tracking. It is divided to 3 blocks which are calibration block, coarse-tuning block and fine-tuning block, and it uses four procedures which are (1) calibration (2) coarse-tuning (3) fine-tuning (4) normal-mode to produce the phase shift amount. This circuit is cell-based, which means that it can be easily replaced to next generation of process, it not only has ability to produce output signal with designated and controllable phase shift to input clock signal, but it has very wide tuning range from 0 to 100ns. In general, temperature will gravely impact this kind of timing control circuit; in circuit without temperature tracking, the more the temperature changes, the more the phase error happens. As a result, the function of temperature tracking is considered necessary in this kind of circuits.. To achieve this function, the generic DLL(delay lock loop) which is different from conventional DLL is presented; with the help of TDC(time to digital converter) as a feedback monitoring two ends of delay line, whole circuit is not operated in open loop in order to track the temperature. According to Nanosim simulation result in TT corner, the phase error without temperature tracking function will be 96ps from 25o c rising to 125o c and this phase error will be reduced from -7ps to 12ps during the temperature changing period when added function of temperature tracking. At last, in same Nanosim simulation in TT corner, this circuit successfully produces from 38ps to 100,036ps with simulating 400 input patterns from whole 10,000 input patterns; although there is offset error of 38ps, the local DNL/INL analysis verify this decent results.

[1] E. Pancera, T. Zwick, and W. Wiesbeck, “Correlation Properties of UWB Radar Target Impulse Response,” IEEE Radar Conf., pp. 1-4, May. 2009.
[2] C. M. Keller, J. M. Burkhart, and T. T. Phuong, “Ultra-Wideband Direct Sampling Receiver,” IEEE Int’l Conf. on Ultra-Wideband (ICUWB), pp. 387-392, 2007.
[3] T. Chalvatzis, T. O. Dickson, and S. P. Voinigescu, “A 2-GHz Direct Sampling Delta-Sigma Tunable Receiver with 40-GHz Sampling Clock and on-chip PLL,” VLSI Circuits, IEEE Symp. on, pp. 54-55, June 2007.
[4] S. Andersson, R. Ramzan, J. Dabrowski, and C. Svensson, “Miltiband direct RF-sampling receiver front-end for WLAN in 0.13 μm CMOS,” Circuit Theory and Design, 2007. ECCTD 2007. 18th European Conf. on, pp. 168-171, Aug. 2007.
[5] H. J. Hsu, and S. Y. Huang, “A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme,” VLSI Systems, IEEE Trans. on, pp. 165-170, Jan. 2011.
[6] M. S. Chen; Hafez, A. A.; C. K. Ken Yang, “A 0.1-1.5GHz 8-bit Inverter-Based Digital-to-Phase Converter Using Harmonic Rejection,” IEEE J. Solid-State Circuits (JSSC), vol. 48, no. 11, p.p. 2681-2692, Nov. 2013.
[7] Hanumolu, P. K.; Kratyuk, V.; G. Y. Wei; and U. K. Moon, “A Sub-Picosecond Resolution 0.5-1.5GHz Digital-to-Phase Converter,” IEEE J. Solid-State Circuit (JSSC), vol. 43, no. 2, p.p. 414-424, Feb. 2008.
[8] J. M. Chou; Y. T. Hsieh; J. T. Wu, “A 125MHz 8b Digital-to-Phase Converter,” IEEE Int’l Solid-State Circuit Conf. (ISSCC), vol. 1, p.p. 436-505, Feb. 2003.
[9] Guoying Wu; Yu, B.; Ping Gui; Moreira P., “Wide-range (25ns) and High-resolution (48.8ps) Clock Phase Shifter,” Electr. Lett., vol. 49, no. 10, p.p. 642-644, May 2013.
[10] C.-W. Tzeng, S.-Y. Huang, P.-Y. Chao, and R.-T. Ding, “Parameterized All-Digital PLL Architecture and Its Compiler to Support Easy Process Migration,” VLSI System, IEEE Trans. on, vol. 22 , no. 3, p.p. 621-630, March 2014.
[11] R. T. Ding, S. Y. Huang, and C. W. Tzeng, “Cell-Based Process Resilient Multiphase Clock Generation,” VLSI Systems, IEEE Trans. on, pp. 1-5, Dec. 2012.
[12] Rong-Jyi Yang, Shen-Iuan Liu, “A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm”, IEEE J. Solid-State Circuits (JSSC), vol.42, pp. 361-373, 2007.
[13] Ke, J. W.; Huang, S.-Y.; Tzeng, C.-W.; Kwai, D.-M; Chou, Y.-F., “Die-to-Die Clock Synchronization for 3-D IC Using Dual Locking Mechanism”, Circuit and System I: Regular Papers, IEEE Trans. on, vol. 60, no. 4, p.p. 908-917, April 2013.
[14] Chen, P.-L.; Chung, C. -C.; Lee, C.-Y., “A Portable Digitally Controlled Oscillator Using Novel Varactors”, Circuit and System II: Express Briefs, IEEE Trans. on, vol. 52, no. 5, p.p. 233-237, May 2005.
[15] J. A. Tierno, A. V. Rylyakov, G. J. English, D. Friedman, and M. Meghelli, “A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65 nm SOI,” IEEE Journal of Solid-State Circuits, vol. 43, pp. 42–51, 2008.
[16] C.-H. Hsu, S.-Y. Huang, D.-M. Kwai, and Y.-F. Chou, "Worst-Case IR-Drop Monitoring with 1GHz Sampling Rate," Proc. of VLSI Design, Automation, and Test (VLSI-DAT), (April 2013).
[17] L. Rodoni et al., “A 5.75 to 44 Gb/s quarter rate CDR with data rate selection in 90 nm bulk CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 7, pp. 1927–1941, Jul. 2009.
[18] M.-S. Chen et al., “A fully-integrated 40-Gb/s transceiver in 65-nm CMOS technology,” IEEE J. Solid-State Circuits, vol. 47, no. 3, pp. 627–640, Mar. 2012.