絕緣層覆矽晶片上平面螺旋電感之研究｜國立清華大學博碩士論文庫

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研究生：	曾嵩弼
論文名稱：	絕緣層覆矽晶片上平面螺旋電感之研究 Study of Planar Spiral Inductors on Ultra-Thin SOI Substrate
指導教授：	葉哲良
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering
論文出版年：	2004
畢業學年度：	92
語文別：	英文
論文頁數：	80
中文關鍵詞：	電感、絕緣層覆矽
外文關鍵詞：	Spiral inductor, SOI
相關次數：	點閱：2 下載：0
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無線通訊是一項不可或缺的技術，它的應用涵蓋軍事、商業、民生、學術等方面。射頻積體電路(RFIC)是一個無線系統中負責收發訊號的電路。而晶片上的電感是RFIC上的一個重要的元件，但它的品質參數一直不佳。品質參數是一項電感效能比較的一個指標。有許多因素會影響電感的品質參數，其中一項重要的因素便是基材效應。因此了解絕緣層覆矽(SOI)晶片上的電感特性便是設計SOI RFIC首先要做的步驟。
在此研究中，利用實驗設計的方法來探討電感的四個設計參數和四種不同的基材的影響。圈數對電感的效能有最顯著的影響，而之後的順序是內徑、線距和線寬。電感在高阻值基材上會比在低阻值基材上有更好的效能，主要是因為減低基材內的各種感應電流。而SOI晶片對電感的影響並不大，因為在薄膜矽層內的位移電流和渦電流都很小。因此以SOI晶片來說，高阻值的SOI會提供電感較好的效能，而且它也與積體電路製程相容。
利用田口實驗計劃法預測最佳電感尺寸，經驗證在2.4GHz的最大品質參數是14.2，而在整個探討頻段(0.1GHz-20.1GHz)的預測最佳電感之效能並不如預期，但仍然能提供一個設計的方向。

On-chip spiral inductor is one important component of RFIC, and suffers from low quality factor which is a figure of merit for performance comparison. There are many factors that affect the quality factor of spiral inductor, and one of the critical factors is the substrate effects. Consequently, understanding the behavior of on-ship spiral inductors on PD (partially depleted) SOI is a necessary step before designing a SOI RFIC.
Four design parameters of spiral inductors and four different substrates were studied in this research by adopting a statistical method – Design of Experiment (DOE). Number of turns has most significant effect on the performance of an inductor, and is followed by inner diameter, spacing, and width. Inductor on high resistive wafer has better performance than it on low resistive wafer because the currents induced in the substrate are reduced. The impact of SOI wafers is minor to the performance of an inductor because small displacement current and small eddy current are induced in the thin silicon layer. High resistive SOI wafer will provide better performance for planar spiral inductors, and it is also IC compatible.
By applying Taguchi method, maximum quality factor at 2.4GHz was predicted and verified to be 14.2, but the maximum quality factor over 0.1GHz to 20.1GHz is not as expected.

CHAPTER 1 PLANAR SPIRAL INDUCTOR........................................................................1
1 INTRODUCTION ............................................................................................................................................... 1
1.1 Research Objective................................................................................................................................. 4
2 THEORY .......................................................................................................................................................... 6
2.1 Structure of Planar Spiral Inductor......................................................................................................... 6
3 LOSS MECHANISMS....................................................................................................................................... 14
3.1 Substrate Coupling Loss........................................................................................................................ 15
3.2 Resistive Loss ....................................................................................................................................... 17
3.3 Radiation Loss...................................................................................................................................... 21
4 EQUIVALENT CIRCUIT MODEL ....................................................................................................................... 22
4.1 Parameters Extraction .......................................................................................................................... 24
4.2 De-embedding ...................................................................................................................................... 25
5 FIGURE OF MERITS........................................................................................................................................ 27
5.1 Q-factor................................................................................................................................................ 27
5.2 Inductance............................................................................................................................................ 27
5.3 Self-resonance Frequency ..................................................................................................................... 28
5.4 FMI....................................................................................................................................................... 28
6 SOI WAFER................................................................................................................................................... 28
6.1 Structure of SOI Wafer.......................................................................................................................... 29
CHAPTER 2 DESIGN OF EXPERIMENT (DOE) ..............................................................31
1 INTRODUCTION ............................................................................................................................................. 31
2 PHASE I PLANNING ....................................................................................................................................... 31
3 PHASE II DESIGNING..................................................................................................................................... 33
4 PHASE III CONDUCTING................................................................................................................................ 35
4.1 Layout................................................................................................................................................... 35
4.2 Fabrication Process .............................................................................................................................. 38
CHAPTER 3 SIMULATION AND EXPERIMENT SETUP ...............................................43
1 INTRODUCTION ............................................................................................................................................. 43
2 SIMULATION.................................................................................................................................................. 43
2.1 Study on SOI Substrate......................................................................................................................... 44
2.2 Study on Substrate Resistivity................................................................................................................ 53
3 MEASUREMENT SETUP.................................................................................................................................. 56
CHAPTER 4 SIMULATION VERIFICATION....................................................................57
1 INTRODUCTION ............................................................................................................................................. 57
2 DESIGN ......................................................................................................................................................... 57
2.1 Metal Pole ............................................................................................................................................ 58
2.2 Patterned Trench Isolation .................................................................................................................... 59
3 SIMULATION, MEASUREMENT, AND MODEL................................................................................................... 60
3.1 Contribution of Currents in Substrate ................................................................................................... 64
4 SUMMARY..................................................................................................................................................... 66
CHAPTER 5 ANALYSIS AND CONCLUSION ...................................................................67
1 PHASE IV ANALYZING................................................................................................................................... 67
1.1 Q at 2.4GHz ......................................................................................................................................... 68
1.2 Maximum Q.......................................................................................................................................... 71
2 PHASE V CONFIRMING.................................................................................................................................. 73
3 CONCLUSION ................................................................................................................................................ 75
4 FUTURE WORKS............................................................................................................................................ 76
REFERENCES........................................................................................................................77

                                

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