二維材料作為新一代半導體材料，相較於傳統矽基晶片展現出顯著優
勢。例如，其晶格結構不含懸鍵，能有效抑制通道厚度縮減時的載子遷移
率退化。此外，在奈米尺度下，二維材料的閘極控制能力優於矽基鰭式場
效電晶體（FinFET），顯示其在“More Moore”技術發展路徑中的潛力。
另一方面，二維材料層間缺乏共價鍵結合，使得機械轉移與精確厚度
控制成為可能。此類材料可透過BEOL 低溫製程進行製造，對底層基板
的選擇性要求極低，因而適用於現有矽製程平台，促進異質整合，並推動
“More than Moore”技術的實現。
然而二維材料電晶體相較於傳統矽製程，在工業化的道路上仍有一些瓶
頸需克服，基於上述技術發展趨勢與研究目標，本論文旨在使二維材料電
晶體的製作方式逐步接近矽基晶片架構，並分為幾個主要階段：
矽基相容製程開發：採用深紫外光微影技術製作二維材料電晶體，縮小
元件尺寸，並開發上閘極結構，以初步展示此邏輯結構之特性能否投入後
續應用。
矽基電晶體匹配元件開發：開發晶圓級大規模二維材料雙閘極電晶體陣
列，透過雙閘極元件，在元件縮小尺度時提供更精確的閘極控制，提高開
關特性，並有效減少短通道效應。並進行三維垂直整合的初步驗證，以評
估其可行性與潛在應用價值。
與矽基元件整合：利用上述技術在矽基鰭式電晶體晶圓上進行垂直異質
整合，實現單晶片式三維邏輯積體電路。

Two-dimensional (2D) semiconductors offer promising potential for post-
Silicon logic devices. Their atomically thin structures and symmetric lattices
prevent mobility degradation from surface scattering and enhance electrostatic
gate control, making them suitable for nanoscale applications. These
attributes align with the “More Moore” paradigm, extending transistor
scalability.
The van der Waals (vdW) bonding in 2D materials facilitates precise
mechanical transfer processes, enabling thickness control and compatibility
with low-temperature back-end-of-line (BEOL) fabrication. Their minimal
substrate selectivity further supports heterogeneous integration with Si
CMOS technology, advancing the “More than Moore”vision. This thesis
encompasses a detailed examination of the aforementioned context and the
advancement of related technologies. It outlines three key stages that bring
2D materials closer to integration with Si-based semiconductor devices.
Si-Compatible Device: Conduct with wafer-level deep ultraviolet (DUV)
photolithography for the fabrication of two-dimensional materials, reduce
transistor dimensions, and develop dual-gate two-dimensional material transistors
to match the characteristics of silicon-based transistors.
Si-Compatible Process: Develop large-scale two-dimensional material
transistor arrays on 8-inch wafers and perform preliminary verification of
three-dimensional vertical integration.
Integration with Silicon-Based Devices: Utilize the aforementioned
technologies to achieve vertical heterogeneous integration on silicon fin
type transistor wafers, enabling the realization of monolithic three-dimensional logic integrated circuits.

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