許多研究顯示，輸入向量(input pattern)很少會通過電路中的長路徑，而這種概念沒有辦法使用傳統的定態時間分析(static timing analysis)來得出。因此在我們的論文中，我們提出了新的時間分析方法，稱為時間漸增方程式(Timed-CDF)，這是一個電路穩定時間所對應的訊號輸入向量的機率分佈圖。我們提出了一個方法來建構出這個時間漸增方程式。首先，我們將訊號輸入向量所對應的電路穩定時間使用一個邏輯方程式來模組，稱為時間特性方程式。在建立特定時間限制的時間特性方程式之後，我們提出了有效率的方程式模擬方法來找出符合時間限制的輸入訊號向量，而這些向量的集合就可以用來產生Timed-CDF。除此之外，我們提出了一個時間限制的選擇方法，來找出更準確的Timed-CDF。並且，我們也考慮了如何產生循序電路特性的輸入訊號向量。平均而言，我們的實驗結果顯示，比使用Verilog來模擬電路快了6.18倍，而在某些電路下，最多可快到16倍。

Many researches have shown that critical paths are rarely activated. The concept of rarely activated cannot be characterized by a static timing analysis. In this thesis, we propose a new timing analysis method called Timed Cumulative Probability Density Function (Timed-CDF). Timed-CDF is a probability distribution of a circuit’s stable time induced by input patterns. We present an efficient way for constructing the Timed-CDF. We formulate input patterns inducing outputs to satisfy a certain time constraint as a Boolean function called Timed Characteristic Function (TCF). After constructing a TCF of a time constraint, an efficient functional simulation will be used to find input patterns, which are used to plot the Timed-CDF. Furthermore, we propose a time constraint selecting method to find more accurate Timed-CDF. A legal input patterns generator is also presented for sequential circuits. On average, our experimental results can be 6.18 faster than Verilog simulation for MCNC combinational benchmarks, and in some cases, up to 16 times faster.

[1]. L. Benini, E. Macii, M. Poncino, and G. De Micheli, "Telescopic units: a new paradigm for performance optimization of VLSI designs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 17, pp. 220-232, 1998.
[2]. Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev Rao, Toan Pham, Conrad Ziesler, David Blaauw, Todd Austin, Krisztian Flautner, and Trevor Mudge, “Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation,” MICRO-36, pp. 7-18, December 2003.
[3]. A. Devgan and C. Kashyap, “Block-based static timing analysis with uncertainty,” ICCAD 2003, pp. 607-614.
[4]. P. Agrawal, V.D. Agrawal, and S.C. Seth, “DynaTAPP: Dynamic Timing Analysis With Partial Path Activation in Sequen- tial Circuits,” Proc. EURODAC, IEEE CS Press, 1992, pp. 138-141.
[5]. J.-J. Liou, K.-T. Cheng, S. Kundu, and A. Krstic, “Fast statistical timing analysis by probabilistic event propagation,” Proc. 2001 Design Automation Conference, pp. 661–666, June 2001. Las Vegas, NV.
[6]. C. Visweswariah et al. ”First-Order Incremental Block-Based Statistical Timing Analysis”. In Procs of DAC, 2004.
[7]. J.J. Liou,et al, “False path aware statistical timing analysis and efficient path selection for delay testing and timing validation”, ACM Design Automation Conference, 2002.
[8]. A. Nadel, “Backtrack Search Algorithms for Propositional Satisfiability: Review and Innovations” Master’s Thesis, the Hebrew University of Jerusalem, 2002.
[9]. S. Devadas, K. Keutzer, and S. Malik, “Computation of floating mode delay in combinational circuit: Theory and algorithms,” IEEE Trans. Computer-Aided Design, Dec. 1993.
[10]. R. Ernst and W. Ye, “Embedded Program Timing Analysis Based on Path Clustering and Architecture Classification,” Proc. IEEE Int’l Conf. Computer-Aided Design, pp. 598-604, 1997.
[11]. P. Ashar, and S. Malik, “Functional Timing Analysis Using ATPG,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1995.
[12]. R. I. Bahar, H. Cho, G. D. Hachtel, E. Macii, and F. Somenzi, “Timing Analysis of Combinational Circuits using ADD’s,” in Proceedings of IEEE European Design Test Conference, pp. 625-629, Feb. 1994.
[13]. S. Devadas, K. Keutzer, and S. Malik, “Computation of Floating Mode Delay in Combinational Circuits: Theory and Algorithms,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 12, pp. 1913-1923, Dec. 1993.
[14]. R. Kundu, and R. D. Blanton, “ATPG for Noise-Induced Switch Failures in Domino Logic,” in Proceedings of the International Conference on Computer-Aided Design, pp. 765-768, Nov. 2003.
[15]. H. Yalcin, and J. P. Hayes, “Hierarchical Timing Analysis Using Conditional Delays,” in Proceedings of the International Conference on Computer-Aided Design, 1995.