本篇論文一共分為五個章節，主要介紹三種無電感式寬頻低雜訊放大器。第二章介紹了一個單端輸入轉差動輸出的寬頻低雜訊放大器。所提出的放大器架構是以反相放大器為基本單位串接組成。此架構有一並聯輸入端與反相輸出端的回授電阻，將有利於寬頻輸入阻抗匹配。此外採用電阻和電容並聯峰值技巧於第三級，能有效改善差動輸出的線性度和增益與相位平衡問題。此電路以台灣積體電路公司 0.18微米互補式金氧化半導體製程製作，量測結果顯示S21 16.4 dB，S11 <-10 dB，輸入端三階交調節點為-8.8 dBm, 最小雜訊指數（含輸出緩衝器）3 dB，整體頻寬為DC-1.4 GHz。差動輸出增益誤差<1.5 dB，差動輸出信號的相位誤差<4.5°。靜態消耗功率為12.8毫瓦。
在第3章中，對轉導增強電容交叉耦合共閘級低雜訊放大器進行了討論。取代傳統外加式電感或是巴倫作為電流源的設計，改以電容交錯耦合架構為電流源，能有效降低雜訊指數，而疊加式電容交錯耦合結構能糾正由於輸入端的巴倫所產生的增益與相位不平衡。基於第三章的討論，第四章提出了以台積電90奈米互補式金氧化半導體製作的低雜訊放大器，達到S21 11.5 dB，S11 <-8.6dB，最低雜訊指數（含緩衝器）2.14dB。而輸入端三階交調節取點為-0.86 dBm，操作頻率在10 M-1.01 GHz。在2 伏特的電壓供應下靜態功耗為5.44 mW。

This thesis consists of five chapters, introducing three topologies of inductor-less wideband low noise amplifier (LNA). Chapter 2 introduces a single to differential wideband LNA. The proposed LNA is composed of three inverter-based gain stages with a global shunt feedback resistor which benefits wideband input impedance matching. Moreover, employing resistor and capacitor (RC) shunt peaking at the third gain stage enhances pseudo-differential output gain and phase balances and linearity. Implemented in TSMC 0.18 μm CMOS process, the proposed LNA covering DC-1.4 GHz achieves a S21 of 16.4 dB, a S11＜-10 dB, IIP3 -8.8 dBm and a minimum noise figure (with output buffer) of 3 dB. The output gain imbalance is less than 1.5 dB and the output phase imbalance is less than 4.5°. The power consumption is 12.8 mW at 1.8 V.
In chapter 3, a transconductance enhancement capacitive cross-coupled (CCC) common-gate LNA is discussed. Adding CCC current source reduces NF, and cascode CCC structure rectifies the gain/phase imbalance due to the input balun. In chapter 4, based on the discussion in chapter 3, the proposed LNA implemented in TSMC 90 nm CMOS process achieves a S21 of 11.5 dB, a S11＜-8.6 dB, minimum noise figure (with buffer) 2.14dB and IIP3 -0.86 dBm from 0.01 to 1.01 GHz. The power consumption is 5.44 mW at 2 V.

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