有鑒於互補式金屬氧化物半導體因特徵尺寸不斷微縮產生新的挑戰，似乎不可避免的必須讓一個高度整合的系統單晶片從一個較低良率的製程開始製作，再透過大量的時間及努力來改善良率以達到合理的高良率水平，三維積體電路整合技術提供了一個新的方法來克服這些設計上的困難並製造價格低廉且有競爭力的系統單晶片。
三維積體電路整合技術可以用來減短可程式邏輯閘陣列關鍵路徑的長度，
一個三維堆疊晶片堆疊數個二維的可程式邏輯閘陣列裸晶粒，並透過穿矽孔及微凸塊做相互連接來達到高封裝密度的目的，然而這個技術同時也帶來了新型的缺陷如穿矽孔的空洞及微凸塊的錯位等，測試這些互連網路的錯誤變得無可避免。在這篇論文中，我們建立了錯誤模型來模擬這些缺陷，根據這些錯誤模型，我們發展了一個錯誤模擬器用來加速錯誤含蓋率的計算，我們提出了一個針對三維可程式邏輯閘陣列互連網路開路、短路及延遲錯誤的自動測試圖樣產生器，這個自動測試圖樣產生器是運用開關陣列拓撲的規律性、有限步階的反覆路徑及繞迴路徑來產生測試路徑，再結合我們所提出的內建式自我測試電路及測試向量，我們可以偵測到互連網路上發生的開路、短路及延遲錯誤。實驗結果顯示，針對不同尺寸的三維可程式邏輯閘陣列，12個測試圖樣已足夠達到100%的開路錯誤含蓋率，偵測所有可能的鄰近短路錯誤，我們需要花費至少40個測試圖樣，而這個數字會隨著三維可程式邏輯閘陣列的高度輕微的增加，我們所提的測試圖樣對可程式邏輯區塊尺寸為50×50×2到50×50×6有很高的延遲錯誤含蓋率(96%)，進而說明了我們方法的可延展性。
為了支持二維及三維可程式邏輯閘陣列的系統，我們提出了一個新的二維可程式邏輯閘陣列延遲錯誤的診斷方案，此方案是以內建式自我測試電路為基礎所開發的，錯誤路徑的位置可以使用改良的內建式自我測試電路找出，這個改良的內建式自我測試電路是將其內部的輸出響應分析器改為掃描串列的形式，因此可以將錯誤資訊用掃描串列的方式傳出來進行分析，再透過對錯誤路徑的分析、錯誤地圖的建立及錯誤線段辨別演算法的使用，我們可以得到可能發生錯誤的線段位置，利用我們所提出的診斷方法可以有效的將真正的錯誤線段找出。我們也提出了一個缺陷錯誤演算法，有效的產生測試路徑來區分單一及成雙缺陷所發生的位置，實驗結果顯示，在一個島形的可程式邏輯閘陣列我們的診斷方法對單一錯誤、成雙錯誤、單一缺陷及成雙缺陷都有很高的診斷解析度。

In view of the challenges encountered by CMOS scaling, it seems inevitable that a highly integrated system on chip (SOC) must start from low production yield, and then it takes tremendous time and effort to improve the yield to a reasonably high level. Three-dimensional (3-D) integration can provide a means to overcome the difficulties in the design and manufacturing of these SOC products.
3-D integration has been touted as an approach to reducing the lengths of critical paths in field programmable gate arrays (FPGAs). A 3-D chip stacks a number of 2-D FPGA bare dies, interconnected by through-silicon vias (TSVs) and micro-bumps, to attain a high packing density. However, the technology also introduces new types of defects, such as TSV void and micro-bump misalignment. Testing the interconnection faults becomes inevitable. In this thesis, we establish the fault models to model these defects. Based on these fault models, we develop a fault simulator to speed up the calculation of fault coverage. We present an automatic test pattern generator for open, short, and delay faults on 3-D FPGA interconnects by exploiting the regularity of switch matrix topology and forming repetitive paths with finite steps and with loop-back. Combining the proposed build-in self-test (BIST) circuit and the test vectors, we can detect the target open, short, and delay fault on interconnects. The experimental results show that 12 test patterns suffice to achieve 100% open fault coverage for different size of the 3-D FPGAs. To detect all possible neighboring short faults needs more than 40 test patterns, whose number increases only slightly with height of the 3-D FPGA. The test patterns have high delay fault coverage (96%) for 3-D FPGAs with the number of configurable logic blocks ranging from 50×50×2 to 50×50×6, demonstrating the scalability of our method.
In support of both 2-D and 3-D FPGA systems, a new BIST-based diagnosis scheme for 2-D FPGA interconnect delay faults is proposed. The faulty paths can be located after configuring the output response analyzer of the BIST circuit as a scan chain. By analyzing the faulty paths, constructing the fault map, and applying the proposed faulty segment identification algorithm, the segment fault candidates can be obtained. The proposed diagnosis scheme can find the effective test paths to locate faulty segment candidates. We also proposed a defect identification algorithm to find the test paths to identify the single and double defects. Experimental results for island-style FPGA show high diagnosis resolution in locating the faulty paths, under the single- and double- fault models caused by single and double defects, respectively.

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