簡易檢索 / 詳目顯示

研究生: 王緒仲
Wang, Hsu-Chung
論文名稱: 通道熱電子注入P型與N型SONOS記憶元件電荷分佈與可靠性分析
The Study of Charge Distribution for programmed p-channel and n-channel SONOS Flash Memories
指導教授: 林崇榮
Lin, Chrong-Jung
金雅琴
King, Ya-Chin
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 產業研發碩士積體電路設計專班
Industrial Technology R&D Master Program on IC Design
論文出版年: 2009
畢業學年度: 97
語文別: 中文
論文頁數: 63
中文關鍵詞: 非揮發性記憶體通道熱電子注入P通道順向讀取反向讀取
外文關鍵詞: NVM, Channel Hot Electron Injection, P-Channel, Forward Read, Reverse Read
相關次數: 點閱:1下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 近年來隨著可攜式電子產品的大眾化,非揮發性記憶體(non- volatile memory, NVM)在製程技術、結構、操作機制以及可靠度上都有著快速的進步。尤其是CMOS製程的微縮,使得矽-氧化矽-氮化矽-氧化矽-矽(silicon-oxide-nitride-oxide-silicon,SONOS)記憶體元件逐漸受到矚目。與傳統的浮動閘極(floating gate)記憶體做比較, SONOS記憶體元件與現今的先進CMOS製程有著高度的整合性,較簡單的結構以及低電壓操作的特性。除此之外,由於電荷能夠局部性地儲存在SONOS記憶體元件的氮化矽層中,使得單一元件具有多位元的儲存能力。了解電荷在氮化矽層中的分佈可以去最佳化寫入操作和減少在擦寫過程中電荷對氧化層的損壞。
    本篇論文主要在比較P通道與N通道SONOS元件在通道熱電子注入(CHEI) 的寫入下所表現出的儲存電荷差異性,並進一部探討兩者間的可靠度。在實驗上,我們採用順向讀取 (forward read) 和逆向讀取(reverse read) 來量測,並分別利用Tsuprem4 和 MEDICI 這兩套TCAD軟體對SONOS元件做製程及電性上的模擬。利用順向讀取和逆向讀取的差異性,藉由放置負電荷在氮化矽層中,比較量測所得到的電流-電壓曲線圖,模擬出P通道與N通道SONOS元件在寫入過程中的電荷分布。得到的實驗結果顯示出通道熱電子在P通道SONOS元件可以均勻地被注入並儲存到氮化矽層,然而在N通道SONOS元件中,電荷卻是局部地被缺陷所束縛。在可靠度上,P通道與 N通道SONOS元件分別經過耐久性(endurance)和電荷保存能力(retention)的測試與比較,P通道SONOS元件因可對通道兩端做均勻地電荷寫入/抹除操作而有較佳的可靠度。


    Recently, with the portable electrical products are popularization, the non-volatile memory (NVM) devices advance fast in fabrication technology, structure, operation condition and reliability. Especially in scaling of CMOS technology, silicon-oxide-nitride-oxide-silicon (SONOS) memory devices become appealing because of their high compatibility with existing advanced CMOS technology, structural simplicity and low-voltage operation as compared to traditional floating gate memory. Besides, due to the charges can be locally trapped in the nitride layer, multi-bit storage in a unit cell can be achieved. Understanding the charge distribution of the nitride layer can help in optimizing the program operation and minimizing the oxide damages in cycling.
    This thesis is studying “the different programmed charge distributions in p-channel and n-channel SONOS devices by channel hot electron injection (CHEI)” and further discusses their reliability. In this experiment, we use the forward and reverse reads to measure the location of charges in the channel, and use TCAD simulation (i.e., Medici) for comparison. Considering the difference between the forward and reverse reads in simulation, we place negative charges in the nitride layer of SONOS devices to fit the measured Id-Vd curves of SONOS devices. The programmed charge distributions of both p-channel and n-channel SONOS devices can be obtained. Therefore The result clearly shows that the channel hot electrons should be uniformly injected and stored in the nitride layer of p-channel SONOS devices, which is very different from what we know in n-channel SONOS devices. In n-channel SONOS devices the charges are locally trapped. In the endurance and retention characterizations, better reliability in p-channel SONOS device is observed as a result of the uniformly bipolar directional stresses during program/erase operations.

    摘要 i Abstract iii 致謝 v 內文目錄 vi 圖表目錄 viii 第一章 緒論 1 1.1 非揮發性記憶體的介紹 1 1.2 浮動閘極快閃記憶體和氮化物補陷記憶體的比較 2 1.3 研究動機 3 1.4 論文大綱 4 第二章 SONOS記憶體的操作機制 8 2.1 寫入與抹除機制 8 2.1.1 N通道SONOS記憶體的寫入 8 2.1.2 P通道SONOS記憶體的寫入 9 2.1.3 福勒–諾得漢(FN)的穿隧抹除 11 2.2 SONOS記憶體元件的讀取機制 11 2.2.1 順向讀取操作 12 2.2.2 反向讀取操作 13 第三章 寫入時的電荷分布情形 24 3.1 量測設備及設定 24 3.2 描繪電荷分布的方法 25 3.3 模擬及量測結果分析 25 3.3.1 P通道SONOS記憶體元件 26 3.3.2 N通道SONOS記憶體元件 28 第四章 可靠度分析 45 4.1 耐久性測試 45 4.2 電荷保存能力分析 46 第五章 結論 56 參考文獻 57

    [1] White, M.H.; Yang Yang; Ansha Purwar; French, M.L., “A low voltage SONOS nonvolatile semiconductor memory technology,” Components, Packaging, and Manufacturing Technology, Part A, IEEE Transactions on Volume 20, Issue 2, June 1997 Page(s):190 – 195
    [2] Barbara De Salvo; Gerardi, C.; van Schaijk, R.; Lombardo, S.A.; Corso, D.; Plantamura, C.; Serafino, S.; Ammendola, G.; van Duuren, M.; Goarin, P.; Mei, W.Y.; van der Jeugd, K.; Baron, T.; Gely, M.; Mur, P.; Deleonibus, S., “Performance and reliability features of advanced nonvolatile memories based on discrete traps (silicon nanocrystals, SONOS),” Device and Materials Reliability, IEEE Transactions on Volume 4, Issue 3, Sept. 2004 Page(s):377 – 389
    [3] Kim, J.-H.; Cho, I.W.; Bae, G.J.; Kim, S.S.; Kim, K.C.; Kim, S.H.; Koh, K.W.; Lee, N.I.; Kang, H.-K.; Suh, K.-P.; Kang, S.T.; Seo, M.K.; Lee, S.H.; Kim, M.C.; Park, I.S., “Highly manufacturable SONOS non- volatile memory for the embedded SoC solution,” VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on 10-12 June 2003 Page(s):31 - 32
    [4] White, M.H.; Adams, D.A.; Bu, J., “On the go with SONOS,” Circuits and Devices Magazine, IEEE Volume 16, Issue 4, July 2000 Page(s):22 – 31
    [5] Swift, C.T.; Chindalore, G.L.; Harber, K.; Harp, T.S.; Hoefler, A.; Hong, C.M.; Ingersoll, P.A.; Li, C.B.; Prinz, E.J.; Yater, J.A., “An embedded 90 nm SONOS nonvolatile memory utilizing hot electron programming and uniform tunnel erase,” Electron Devices Meeting, 2002. IEDM '02. Digest. International 8-11 Dec. 2002 Page(s):927- 930
    [6] Myung Kwan Cho; Kim, D.M.,“ High performance SONOS memory cells free of drain turn-on and over-erase: compatibility issue with current flash technology,” Electron Device Letters, IEEE Volume 21, Issue 8, Aug. 2000 Page(s):399 - 401
    [7] B. Eitan et al., “Can NROM, a 2 bit, trapping storage NVM cell, give a real challenge to floating gate cells?,” in Ext. Abst. 1999 Conf. Solid State Devices and Materials, Tokyo, Japan, 1999, pp. 522–524.
    [8] Eitan, B.; Pavan, P.; Bloom, I.; Aloni, E.; Frommer, A.; Finzi, D., “ NROM: A novel localized trapping, 2-bit nonvolatile memory cell,” Electron Device Letters, IEEE Volume 21, Issue 11, Nov. 2000 Page(s):543 – 545
    [9] Tsai, W.J.; Gu, S.H.; Zous, N.K.; Yeh, C.C.; Liu, C.C.; Chen, C.H.; Tahui Wang; Pan, S.; Chih-Yuan Lu,“ Cause of data retention loss in a nitride-based localized trapping storage flash memory cell,” Reliability Physics Symposium Proceedings, 2002. 40th Annual 7-11 April 2002 Page(s):34 – 38
    [10] Janai, M.; Eitan, B.; Shappir, A.; Lusky, E.; Bloom, I.; Cohen, G., “Data retention reliability model of NROM nonvolatile memory products,” Device and Materials Reliability, IEEE Transactions on Volume 4, Issue 3, Sept. 2004 Page(s):404 - 415
    [11] Huiqing Pang; Liyang Pan; Lei Sun; Dong Wu; Jun Zhu, “Trapped Charge Distribution during the P/E Cycling of SONOS Memory,” Physical and Failure Analysis of Integrated Circuits, 2006. 13th International Symposium on the July 2006 Page(s):84 – 87
    [12] Tsai, W.J.; Zous, N.K.; Chou, M.H.; Huang, S.; Chen, H.Y.; Yeh, Y.H.; Liu, M.Y.; Yeh, C.C.; Wang, T.; Ku, J.; Chih-Yuan Lu, “Cause of erase speed degradation during two-bit per cell operation of a trapping nitride storage flash memory cell,” Reliability Physics Symposium Proceedings, 2004. 42nd Annual. 2004 IEEE International. 25-29 April 2004 Page(s):522 - 526
    [13] Mori, E. Sakagami, H. Araki, Y. Kaneko, K. Narita, Y. Ohshima, N.Arai and K. Yoshikawa," ONO Inter-poly Dielectric Scaling for Nonvolatile Memory Applications", IEEE Trans. on Electron Dev. Vol.38, No.2,Feb.1991.
    [14] C.Hu, “Lucky-electron model of hot-electron emission,” in IEEE International Electron Device Meeting, p.22-p.25,1979
    [15] H.M. Lee; S.T. Woo; H.M. Chen; R. Shen; C.D. Wang; L.C. Hsia;
    C.C.-H. Hsu,“ NeoFlash - True Logic Single Poly Flash Memory Technology,” Non- Volatile Semiconductor Memory Workshop, 2006. IEEE NVSMW 2006. 21st 2006 Page(s):15 – 16
    [16] T.-C. Ong, P.K. Ko and Chenming Hu, “Modeling of substrate current in p-MOSFET’s,” IEEE Electron Device Letter, vol.-8, no.9., p.413-p.416,1987
    [17] T.-C. Ong, K. Seki, P.K. Ko, and Chenming Hu, “P-MOSFET gate current and device degradation,” in IEEE International Reliability Physics Symposium, p.178-p.182, 1989
    [18] Y. Taur and T. H. Ning, “Fundamentals of Modern VLSI Devices”, pp. 97.
    [19] Selmi, L.; Sangiorgi, E.; Bez, R.; Ricco, B., “ Measurement of the hot hole injection probability from Si into SiO 2 in p-MOSFETs,” Electron Devices Meeting, 1993. Technical Digest., International 5-8 Dec. 1993 Page(s):333 - 336
    [20] Ng, K.K.; Taylor, G.W., “Effects of hot-carrier trapping in n- and p-channel MOSFET's,” Electron Devices, IEEE Transactions on Volume 30, Issue 8, Aug 1983 Page(s):871 - 876
    [21] M.Lenzlinger and E.H.Snow, “Fowler-Nordheim tunneling into thermally grown SiO2,” Journal of Applied Physics, vol.40, no.1, p.278-p.283, 1969
    [22] Z.A.Weinberg, “On tunneling in MOS structure, “ Journal of Applied Physics, vol.53, p.5052, 1982
    [23] Perniola, L.; Bernardini, S.; Iannaccone, G.; De Salvo, B.; Ghibaudo, G.; Masson, P.; Gerardi, C.,“ Electrostatic effect of localized charge in dual bit memory cells with discrete traps,” Solid-State Device Research conference, 2004. ESSDERC 2004. Proceeding of the 34th European 21-23 Sept. 2004 Page(s):249 - 252
    [24] T. A. Fjeldly and M. Shur, “Threshold voltage modeling and the subthreshold regime of operation of short-channel MOSFET’s,” IEEE Trans. Electron Devices, vol. 40, pp. 137–145, Nov. 1993.
    [25] Eli Lusky, Assaf Shappir, Guy Cohen, Ilan Bloom,Meir Janai, Eduardo Maayan, Oleg Dadashev, Yoram Betser, Yan Polansky, Shai Eisen, Yair Sofer and Boaz Eitan, “NROM Technology (Excerpt from IEEE book on NVM Technologies)”, Retrieved November 22,2008, http://www.saifun.com/objects/NROM_ Technology_experts_from_IEEE_book_on_NVM_Technologies.pdf
    [26] Kumar, P.B.; Nair, P.R.; Sharma, R.; Kamohara, S.; Mahapatra, S.,“ Lateral profiling of trapped charge in SONOS flash EEPROMs programmed using CHE injection,” Electron Devices, IEEE Transactions on Volume 53, Issue 4, April 2006 Page(s):698 - 705
    [27] Lusky, E.; Shacham-Diamand, Y.; Bloom, I.; Eitan, B., “Characterization of channel hot electron injection by the subthreshold slope of NROMTM device”, Electron Device Letters, IEEE Volume 22, Issue 11, Nov. 2001 Page(s):556 – 558
    [28] Larcher, L.; Verzellesi, G.; Pavan, P.; Lusky, E.; Bloom, I.; Eitan, B., “ Impact of programming charge distribution on threshold voltage and subthreshold slope of NROM memory cells” Electron Devices, IEEE Transactions on Volume 49, Issue 11, Nov. 2002 Page(s):1939- 1946
    [29] Aritome, R. Kirisawa, T. Endoh, N. Nakayama, R. Shirota,
    K. Sakui,K. Ohuchi and F. Masuoka,” Extended Data
    Retention Characteristics After more Than 10e4 Write and
    Erase Cycles in EEPROMs”,International Reliability
    Physics Symp., P.259, 1990.
    [30] Aritome, S.; Shirota, R.; Hemink, G.; Endoh, T.; Masuoka, F.,“Reliability issues of flash memory cells,” Proceedings of the IEEE Volume 81, Issue 5, May 1993 Page(s):776 - 788

    無法下載圖示 全文公開日期 本全文未授權公開 (校內網路)
    全文公開日期 本全文未授權公開 (校外網路)

    QR CODE