隨著積體電路製程技術的進步，從0.25微米製程進入0.18甚至是0.09深次微米製程,也因此導致關於時序(Timing)所引起的製程缺陷(Manufacturing Defects)將漸漸的主宰了晶片的良率(Yield)，然而，利用傳統針對Stuck-at Fault所加入可測試性設計(Design for Testability)的測試方法，諸如掃描串聯測試(Scan Chain Testing)以及內建自我測試(Built-in Self-testing)來測試時序缺陷並不適合。此外，針對上述方法缺點而研發的軟體介面功能性測設(Software-based Functional Testing)在處理較複雜的大型電路，例如處理器(Processors)或是功能導向積體電路(ASICs)卻顯得費時而無效率可言。在此篇論文，我們提出一個改善軟體介面功能性測試缺點並針對時序缺陷之一的路徑延遲錯誤(Path Delay Fault)的功能性路徑延遲性錯誤測試流程(Functional Path Delay Fault Test Flow)，並且針對較複雜
功能性限制的擷取(Functional Constraints Extraction)加以自動化。
測試的流程主要分成四個部分，第一部分，根據路徑延遲測試的定義將一個循序數位邏輯電路(Sequential Logic Circuit)自動分割成數個管線級(Pipeline Stage)．第二部分，則是藉由自動分析硬體描述語言(RTL code)，處理器指令集(Instruction Set Architecture)以及測試樣板(Testbench)，以萃取出每個管線級可能的輸入限制(Inputs Constraints)，這些限制描述著微處理器在執行指令的過程可能的輸入組合．接著在第三部分，利用兩套商業軟體作為輔助，藉由TetraMax針對PrimeTime所擷取出的延遲路徑來作自動樣本的產生(Automatic Test Pattern Generation)，所得到的測試樣本(Test Patterns)將與第二部分所萃取的功能性限制作比對與篩選，將符合的限制條件的測試樣本篩選出來．第四部份為測試樣本轉換(Test Patterns Translation)，將符合條件的測試樣本轉合成為一個可執行的程式，經由測試程式將測試樣本輸送到帶測管線級作測試。最後本文以Parwan處理器進行測試流程的開發與驗證，以自動化的提升次是流程效率。

With the advantages of at-speed testing, functional mode operation and low area overhead, functional self-test approach is wildly adopted nowadays for delay fault testing. However, modern designs will make this approach hard to apply due to large gate counts and complex functionality. Thus, a modified functional test flow is proposed by this paper to test processors and could be extended to ASICs. This flow includes circuit partition, constraints extraction, pattern generation and back-trace. Each part of the proposed flow is more automatic and effective than other method. The experiment result is demonstrated by testing Parwan processor. And the result showed is good by the proposed method.

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