在電源轉換模式下考慮多餘脈衝現象的一個有效率睡眠電晶體喚醒排程

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研究生：	陳昱廷 Yu-Ting Chen
論文名稱：	在電源轉換模式下考慮多餘脈衝現象的一個有效率睡眠電晶體喚醒排程 An Efficient Wake-up Schedule during Power Mode Transition Considering Spurious Glitches Phenomenon
指導教授：	張世杰 Shih-Chieh Chang
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2007
畢業學年度：	95
語文別：	英文
論文頁數：	41
中文關鍵詞：	低功率設計、漏電流、睡眠電晶體、電源轉換模式、浪湧電流、喚醒排程
外文關鍵詞：	low power, leakage, sleep transistor, power mode transition, surge current, wake-up schedule, power-gating, MTCMOS, DSTN, wake-up time
相關次數：	點閱：2 下載：0
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在先進製程中，漏電流呈現指數成長，逐漸在整體功率消耗中佔有主要的部份。在降低漏電流的技巧中，功率閘門(power-gating)的技巧是其中最有效的方法之一，在此技巧中，高門檻電壓(high Vth)的睡眠電晶體會和低門檻電壓(low Vth)的邏輯元件會依不同的架構而有不同的擺放方式。在功率閘門的技巧中有兩種運作模式，在活動模式(active mode)下，睡眠電晶體會被打開以維持電路的正常運作；在睡眠模式(sleep mode)下，睡眠電晶體會被關上以減少漏電流的損耗。
當電路由睡眠模式轉換到活動模式時，會有一段時間電路是無法正常運作的，這段時間我們稱為電源轉換模式(power mode transition)。在電源轉換模式下，由於睡眠電晶體的開啟，一個很大的放電電流，我們稱之為浪湧電流(surge current)會產生，過大的浪湧電流會造成雜訊，並導致電源閘極設計產生錯誤。其中一個有效控制此浪湧電流的方法是針對睡眠電晶體的開啟順序作排程。在這篇論文中，我們介紹了許多關於浪湧電流的重要特性。這些特性是針對在分散式睡眠電晶體網路(Distributed Sleep Transistor Network)這種架構上，此架構在工業界被廣為使用。根據這些特性，我們提出精確的浪湧電流估算，並提供一個有效率的排程在分散式睡眠電晶體網路上。根據實驗數據顯示，我們的結果和前人相比有非常顯著的進步。平均而言，在電源轉換模式下，我們的結果可減少366倍的喚醒時間，並降低39.76%的能量耗損。

During the power mode transition, a large surge current may lead to the malfunctions in a power-gating design. One efficient way to control the surge current is to schedule the turn-on sequences of sleep transistors. In this paper, we introduce several important properties of the surge current during the power mode transition for the Distributed Sleep Transistor Network (DSTN) designs, which is a popular power gating design style. Based on these properties, we propose an accurate estimation of surge current and provide an efficient schedule on the DSTN structure. Our experiment achieved significantly better results than previous works—on average, 366 times wake-up time reduction and 39.76% less energy loss during the power mode transition.

List of Contents:
Abstract    i
Contents    ii
List of Figures    iii
List of Tables    iv
Chapter 1 Introduction    1
Chapter 2 Preliminaries    8
Chapter 3 Surge Current Analysis    11
3.1. Surge Current versus Wake-up Time    12
3.2. Problem Formulation    15
3.3. Surge Current versus Virtual Ground    16
Chapter 4 Wake-up Schedules for Wake-up Time Minimization Considering Spurious Glitches    18
4.1. An Efficient Wake-up Schedule for Wake-up Time Minimization    19
4.2. Spurious Glitches Phenomenon    24
4.3. An Intellignet Wake-up Schedule for Spurious Glitches Minimization Considering Physical Implementation    28
Chapter 5 Implementation Flow    32
Chapter 6 Experimental Results    35
Chapter 7 Conclusions    39
References    40

List of Figures:
Figure 1: A DSTN power gating structure    2
Figure 2: Two surge current distributions under two wake-up schedules: All-On and One-by-One    4
Figure 3: Spurious glitches of an industrial design during the power mode transition    6
Figure 4: Current distribution of the DSTN design    9
Figure 5: Wake-up time comparison under two different schedules    13
Figure 6: Wake-up schedule problem formulation    15
Figure 7: Two segments of the virtual ground of an industrial design    17
Figure 8: Our wake-up schedule example    20
Figure 9: Wake-up schedule algorithm    23
Figure 10: Two wake-up schedules' example    25
Figure 11: A turned-on sequence considering the physical placement of sleep transistors    29
Figure 12: Intelligent wake-up schedule algorithm    31
Figure 13: Implementation flow    33


List of Tables:
Table 1: The comparisons among Wake-up Time, Energy Loss, and Surge Current    37

                                

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