為了高速網路傳輸的需要，高速、低功率消耗的串列多工器(Parallel-to-Serial Multiplexer）在I/O介面中更顯得重要。其主要功能，是將許多低速平行態的資料匯流排轉為一個高速串列訊號並傳輸之。為了解決傳輸時DC平衡的問題，8B/10B的編碼方式大量的運用在網路傳輸中，不論是編碼後或是未編碼的資料，16/20:1的串列多工器能一次處理兩個位元組的傳輸。
在本論文中，提出了一個混合了樹狀結構與位移暫存器的16/20:1四分之一頻率串列多工器，此串列多工器能降低大部分電路區塊的操作頻率，將所需的時脈頻率降低至傳輸速度的四分之一，讓電路的設計更簡單、更穩定且低功率。在較低速的電路區塊中，採用Full Swing的TSPC暫存器來實現，對雜訊的容忍程度較強且能降低功率消耗。而在較高速的區塊，則採用Differential型態的高速電流型邏輯閘來實現。這樣的架構能在速度、穩定度與功率消耗中取得較好的平衡。
對於高速電路的設計而言，除了架構之外，在元件尺度的研究非常的重要。TSMC提供了兩種元件：RF與Baseband元件。RF元件適合高速運作的電路，對雜訊有較好的抵抗程度，其缺點為大量的面積消耗。而Baseband元件則適合在較低頻運作，面積小是其優點。本論文對此兩種元件作了詳細的研究，並提出修改過、較省面積的RF元件，保留原始RF元件良好的高頻表現與抵抗雜訊能力，同時縮減了所需的面積消耗。
本論文所提出的兩個16/20:1四分之一頻率串列多工器，其一使用了TSMC 0.18um的製程，所有的電晶體均使用節省面積的RF元件，可達到6Gbps的傳輸速度與10 ps的訊號抖動。另一個則使用TSMC 0.13um的製程，混用了節省面積的RF元件與傳統的Baseband元件，讓面積大幅縮減，同時可達到8.8Gbps的傳輸速度與18 ps的訊號抖動，其面積僅為在0.18um製程中完全使用節省面積RF元件的23.2%。
用0.18um製程設計的串列多工器，已整合到一個SERDES晶片中，此晶片的量測結果可達到5.12Gbps的資料傳輸速度。而採用0.13um製程的串列多工器，則整合到一個 4 x 4 STDM Switch IC中，根據其佈局後模擬結果，每個Channel可達到7Gbps的資料傳輸速度，整體速度為 28Gbps / 4ch。

For high speed network transmission, the high speed low power multiplexer is more important in I/O interface. The main function of the multiplexer is to serialize many parallel buses into a serial link. To overcome the DC balance problem during data transmission, the 8B/10B encoder is often used for network transmission. The 16/20:1 multiplexer can do two bytes serialization at the same time for the data encoded or not.
In this thesis, a quarter-rate 16/20:1 multiplexer mixed with the tree-based type and the shift-register type is proposed. The operation frequency of most blocks is only one-fourth to the output data rate. That makes the circuit more easily to design, more stable and lower power consumption. For those low speed blocks, the full swing TSPC registers are used. Its noise tolerance is better and the power dissipation is reduces. For the high speed blocks, the differential type current mode logic (CML) is adopted. This architecture achieves better balance among the speed, stability and power dissipation.
For the design of high speed circuits, the study at device level is very important besides the architecture. TSMC provides two devices: the RF device and the baseband device. The RF device is suitable for high speed circuits, its noise shielding is better with the drawback of huge area consumption. The baseband device is good for low speed circuits; smaller area is the advantage. This thesis studies these devices in detail, and proposes the area-saving RF device with lower area consumption. The area-
saving RF device reserves the advantage of the RF device with good performance at high speed operation and good noise shielding; furthermore, the area is reduced.
Two quarter-rate 16/20:1 multiplexers are proposed in this thesis. One is based on the TSMC 0.18um technology; all transistors are the area-saving RF devices. It can achieve the 6Gbps data rate with 10 picoseconds jitter. The other is based on the TSMC 0.13um technology; the architecture is mixed with the area-saving RF devices and the baseband devices to reduce the area. Its maximum data rate is 8.8Gbps with 18 picoseconds jitter. The area is only 23.2% to that with all area-saving RF devices.
The multiplexer designed with 0.18um technology is integrated into a SERDES chip. The measurement result shows that it can achieve 5.12Gbps data rate. For that with 0.13um technology, it is integrated into a 4 x 4 STDM Switch IC. Based on the post-simulation result, the maximum speed can achieve 7Gbps data rate. Overall speed is 28Gbps / 4ch.

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