LDMOS做為Power ICs中最常使用的功率元件，其效能會影響電路的效率，一般對於LDMOS效能的評量常以特徵導通電阻(Specific on-resistance, R_(on,sp ))與崩潰電壓為主，較少討論元件的動態特性與可靠度。本論文主要利用TCAD模擬來分析元件分別在上橋與下橋操作情形下電壓、電場以及電流的分布情形，並比較其中的異同。之後再針對元件結構設計進行調整並搭配TCAD模擬以及實際量測確認結構的改變對元件特性的影響，最後再透過熱載子應力測試來確認元件的可靠度。
實際量測結果顯示，Split gate結構可以大幅降低元件開啟時所需的電荷量，降幅約為40%，對於切換速度的提升有所幫助。崩潰電壓的部分隨著元件閘極與汲極間距離加長，耐壓可以有所提升，若在汲極端加上NWIO結構可以使閘極電壓3.3伏特時的崩潰電壓上升14.1%。在可靠度的部分，量測結果顯示Split gate結構與汲極端加NWIO結構的考靠度表現皆不會比標準結構差。綜合來說以Split gate搭配汲極端加上NWIO結構並選擇適當的閘極與汲極間距離可以有最均衡的元件特性。

The performance of a LDMOS is critical to the efficiency of Power ICs, since it is the most widely used power device in these applications. LDMOS is typically evaluated by R_(on,sp) and breakdown voltage and its dynamic characteristics and reliability are also intensively studied. The main objective of this thesis is using TCAD simulation to analyze the voltage, electric field and current distribution device LDMOS in the high-side and low-side operation conditions, and compare the similarities and differences. Then, some different structures are simulated and measured to confirm the predicted influences of the structure change on the electrical characteristics. Finally, the reliability of the devices are investigated through the hot carrier stress.
The measurement results show that split gate can reduce 40% the amount of gate charge required during the device turn on, which is helpful for the improvement of the switching speed. As the distance between gate and drain of the device increases, the breakdown voltage can increase. If NWIO implant is added at drain side, the breakdown voltage at a gate voltage of 3.3 volts can be increased 14%. As for the reliability, measurement results show that the reliability performance of split gate and NWIO drain side structure is comparable to the standard structure. In short, combining split gate and NWIO drain side with an appropriate gate drain distance can have the most balanced device characteristics.

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