由於在通訊系統中高速傳輸速率的需求，電流型邏輯電路的使用漸漸成為一項趨勢。雖然電流型邏輯電路擁有高速的傳輸效能，卻因為結構中持續供應的電流源而產生了可觀的靜態功率消耗。然而，在傳統電流型邏輯電路中，功率消耗及延遲時間的乘積並不隨著操作電壓的下降而變小，即：在功率消耗及延遲時間之間比須有所取捨。因此，對傳統的電流型邏輯電路而言，欲使用一般降低功耗的技術來節省耗能並且維持原本的高速傳輸速率是很困難的。
近年來，有一些針對電流型邏輯電路所研究的低功耗技術被發表。然而，他們不是犧牲了原本差動式輸出訊號的電壓擺幅，就是犧牲了原本應有的傳輸速率，以換取低耗能的電流型邏輯電路。也就是說，這些方法並不能解決電流型邏輯電路本質上的問題。
在此論文中，提出了一個可適性主體偏壓的輔助電路來實現超低功耗的電流型邏輯電路。在這項設計中，主體偏壓可以依據差動式輸入訊號來自動調整，並且提供給電流型邏輯電路裡的輸入源極耦合對。藉由交替切換主體偏壓，差動式輸出訊號的電壓擺幅增大，進而製造了用來降低操作電壓來節省功耗的空間。
經由利用時脈電源的觀念所設計的可適性主體偏壓輔助電路，操作電壓可大幅降低，同時電路仍可維持原本差動式輸出訊號的電壓擺幅及原本電路的傳輸速率。本電路結構克服了電流型邏輯電路中，功耗與速度的乘積為常數的限制，並可節省最高60%，平均50％的功率消耗。在內文中將呈現由可適性主體偏壓所設計之超低功耗緩衝器、多工器及鎖存器的設計方法和效能分析。同樣的設計概念也可延伸套用至由差動式輸入訊號所組成的電路。

With the demand of high transmission rate, there is a tendency toward current-mode logic (CML) circuits in communication systems. Although CML circuits are of high speed performance, the sustained current source consumes static power substantially. However, because the power-delay product (PDP) of the conventional CML circuits is approximate to a constant with varying supply voltage, i.e. the power-delay tradeoff, the conventional CML circuits is difficult to reducing power dissipations while maintaining high speed through the traditional low power techniques.
In the recent years, there have been some low power methodologies published for CML circuits. However, they save power consumption either by scarifying swing voltage of differential output signals or by losing high speed performance. It means that the intrinsic problem of the conventional CML circuits has not been broken through yet.
In this thesis, a novel adaptive body biasing (ABB) circuit is proposed for ultra low power CML circuits. In the design, body bias self-adjusts depending on the differential input signals and applies to the source-coupled pairs in CML circuits. By switching body bias alternately, the margin for lowering power through reducing supply voltage VDD is originated from the increased voltage swing of the differential output signals.
Through the proposed clocked-power ABB circuit, the supply voltage VDD and the dc-level of the differential inputs can be reduced significantly while maintaining the original voltage swing of differential output signals and the original transmission rate. The architecture can reach power saving up to 60%, and 50% on average with the breaking of power-delay tradeoff. The design methodology and performance analysis for the low power ABB CML Buffers, MUXs, and Latches are presented in the thesis. The same design concept can also be extended to circuits composed of differential input pairs.

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