應用於無線通訊之快速鎖定自動增益控制迴路

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研究生：	張益韶 Yi-Shao Chang
論文名稱：	應用於無線通訊之快速鎖定自動增益控制迴路 A Fast-Locking Automatic Gain Control Loop for Wireless Communication Applications
指導教授：	柏振球 Jenn-Chyou Bor
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2007
畢業學年度：	96
語文別：	中文
論文頁數：	105
中文關鍵詞：	自動增益控制迴路、可變增益放大器、振幅偵測器
外文關鍵詞：	Automatic gain control loop, Variable gain amplifier, Amplitude detector
相關次數：	點閱：3 下載：0
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在這篇論文中，使用了0.18um CMOS製程去實現應用於無線通訊的快速鎖定的自動控制增益迴路。在這個迴路中，採用了兩個概念去加快整個迴路的鎖定時間。首先，使用I/Q兩條路徑的四個各相差九十度相位的訊號，以及採用三角函數中的平方公式,正弦平方與餘弦平方和為一 ,去消除交流訊號的振幅，再送到比較器中與比較的電壓相比，進而去改變放大器的增益，而不是使用傳統的低通濾波器，可以增加準確度與加快鎖定速度；第二，為了能較簡單地去改變迴路中的增益值並減少電容的面積，在自動控制增益迴路中的反饋路徑是採用數位的方式去實現。

此量測晶片的面積是1.113 mm × 0.918 mm。在自動控制增益迴路中的可變增益放大器可以提供約為60 dB的增益範圍從-5.88 dB到 53.94 dB，同時，在最大增益的設定下，有24.1 MHz的頻寬。在最小頻寬的設定下，全諧波失真(THD)與IIP3，各是32.14 dBc與0.3 dBV。當輸入陣幅是0V到0.4V時，振幅偵測器的輸出範圍是從1.437V到1.11V。在輸入訊號頻率為1 MHz的前提下，自動控制增益迴路的鎖定時間大約是18.4 μs ，同時在輸出振幅是0.8 Vppd的情況下，鎖定增益範圍是 -4 dB 到 40 dB。總耗電流是13.4mA。

In this thesis, a fast-locking automatic gain control loop is implemented in 0.18μm mixed-mode CMOS technology for wireless communication applications. This loop adopts two concepts to enhance the fast-locking time. First, I/Q paths and the squaring function of Giordano, , are used to cancel AC ripple rapidly, instead of using low pass filter. Second, the feedback path of AGC loop is implemented with digital circuit for easily changing loop gain and reducing the capacitance area.

The area of the experimental chip is 1.113 mm × 0.918 mm. The VGA in the AGC loop provide 60 dB gain range from -5.88 dB ~ 53.94 dB and has 24.1 MHz bandwidth at maximum gain setting. The total harmonic distortion (THD) and input referred IP3 at minimum gain setting are 32.14 dBc and 0.3 dBV. The tuning range of amplitude detector is from 1.437 V to 1.11 V when input signal amplitude is from 0 V to 0.4 V. The locking time of the AGC loop is less than 18.4 μs when the input signal operates in 1 MHz and the locking gain range is -4 dB ~ 40 dB and output swing is 0.8 Vppd.

Contents
Chapter 1 ......................................................................................................................1
Introduction..................................................................................................................1
1 Motivation.................................................................................................1
2 Receiver Architecture..............................................................................2
3 Thesis Organization.................................................................................5
Chapter 2 ......................................................................................................................6
Overview of Automatic ................................................................................................6
Gain Control .................................................................................................................6
1 AGC Schemes .................................................................................................6
1.1 Feedforward Gain Control ....................................................................7
1.2 Feedback Gain Control .........................................................................8
2 Feedback-Type AGC Loop Analysis...........................................................11
2.1 Linearized model and Mathematical analysis.....................................12
First-order linearized model.........................................................................12
2.2 Stability and Loop Bandwidth ............................................................15
2.3 Locking Time Analysis .......................................................................16
3 Proposed AGC Loop Architecture..............................................................19
3.1 Feedback-Type AGC Loop .................................................................19
3.2 Fast-Locking Technique......................................................................20
3.3 DC Offset Cancellation.......................................................................21
4 Summary.......................................................................................................22
Chapter 3 ....................................................................................................................23
Design of AGC Analog/Mixed-Mode Blocks .............................................................23
1 VGA.........................................................................................................23
1.1 VGA Architecture ...............................................................................24
1.2 DC Offset Control ...............................................................................34
2 Amplitude Detector......................................................................................35
2.1 Flipped voltage follower cell ..............................................................35
2.2 Squaring Circuit ..................................................................................36
2.3 AC Ripple Elimination........................................................................38
3 Comparator, Bias Circuit, and Output Buffer..........................................42
3.1 Comparator .........................................................................................42
3.2 Bias Circuit .........................................................................................43
3.3 Output Buffer ......................................................................................45
VII
4 Simulation Results .......................................................................................46
4.1 VGA Simulation Result .....................................................................46
5 Summary.......................................................................................................55
Chapter 4 ....................................................................................................................56
Design of AGC Digital ...............................................................................................56
Feedback Loop ...........................................................................................................56
1 Gain Control Feedback Loop ...............................................................56
1.1 Digital Filter........................................................................................58
1.2 SAR/Linear Gain Control Schemes ....................................................59
1.3 Adaptive-Loop control ........................................................................60
2 DC Offset Cancellation Loop................................................................64
3 Simulation Result ...................................................................................65
4 Summary.................................................................................................65
Chapter 5 ....................................................................................................................66
AGC System Simulation and Measurement Results ..............................................66
1 AGC System Simulation........................................................................66
1.1 Behavior Model Simulation................................................................66
1.2 Mixed-Mode Circuit Simulation.........................................................71
2 Chip Measurement Result.....................................................................74
2.1 Measurement Setup.............................................................................74
2.2 Measurement Results .........................................................................76
Chapter 6 ..................................................................................................................102
Conclusions and Future Works ..............................................................................102
Bibliography .............................................................................................................103

                                

[1] Elwan, H.O.; Tarim, T.B.; Ismail, M., “A digitally controlled dB-linear CMOS AGC for low voltage mixed signal applications,” IEEE CNF, Circuits and Systems, 1998. Proceedings. 1998 Midwest Symposium on 9-12 Aug. 1998 Page(s):423 – 425

[2] Shoji Otaka, Gaku Takemura, and Hiroshi Tanimoto, “A Low-Power Low-Noise Accurate Linear-in-dB Variable-Gain Amplifier with 500-MHz Bandwidth,” IEEE Journal of Solid-Stats Circuits, vol. 35, no. 12, Dec. 2000

[3] B. Razavi, “Design Considerations for Direct-Conversion Receivers,”IEEE Trans. On Circuits and Systems II, pp. 428 -435, Jun. 1997.

[4] C.-K. Wang and P.-C. Huang, “An Automatic Gain Control Architecture for SONET OC-3 VLSI,” IEEE Trans. on Circuits and Systems II, vol. 44, no. 9, pp. 779-783, Sep. 1997.

[5] J. M. Khoury, `` On the Design of Constant Settling Time AGC Circuits,'' IEEE Tran. Circuits and Systems, Part II, Vol. 45, pp. 283-294, Mar. 1998.

[6] C-C Hsu and J-T Wu, ``A Highly Linear 100-MHz CMOS Programmable Gain Amplifier,'' 2001 IEEE International Symposium on Circuits and Systems, pp. 647-650, May. 2001.

[7] C.-K. Wang, P.-C. Huang and C.-Y. Huang, “A BiCMOS Limiting Amplifier for SONET OC-3,” IEEE Journal of Solid-State Circuits, vol. 44, no. 8, pp.1197-1200, Aug. 1996.

[8] Chien-Chih Lin; Muh-Tain Shieu; Chorng-Kuang Wang, “A dual-loop automatic gain control for infrared communication system,” IEEE CNF, ASIC, Proceedings. 2002 IEEE Asia-Pacific Conference on6-8, Page(s):125 – 128, Aug, 2002.

[9] C.-S. Wang and P.-C. Huang, “A CMOS Low-IF Programmable Gain Amplifier with Speed-Enhanced DC Offset Cancellation,” IEEE Asia-Pacific Conf. on ASIC, Taipei, Taiwan, Aug. 2002.

[10] Yi-Huei Chen; Jenn-Chyou Bor; Po-Chiun Huang, “A 2.5 V CMOS switched-capacitor channel-select filter with image rejection and automatic gain control,” IEEE CNF, Radio Frequency Integrated Circuits (RFIC) Symposium, 2001.

[11] Chung-Wei Lin; Yen-Zen Liu; Hsu, K.Y.J, “A low distortion and fast settling automatic gain control amplifier in CMOS technology”, IEEE CNF, .;
Circuits and Systems, ISCAS '04.Page(s):I - 541-4 Vol.1, May 2004

[12] Rijns, J.J.F.”CMOS Low Distortion High Frequency Variable Gain Amplifier, ”IEEE J. Solid-State Circuits, Vol.31,pp.1029 - 1034,Jul. 1996

[13] Demosthenous, A.; Panovic, M. “Low-voltage MOS linear transconductor/squarer and four-quadrant multiplier for analog VLSI”, IEEE Journal of Solid-State Circuits, Volume 52, Issue 9, Sept. 2005 Page(s):1721 – 1731, 2005

[14] Ramirez-Angulo, J.; Carvajal, R.G.; Torralba, A.; Galan, J.; Vega-Leal, A.P.; Tombs, J. “The flipped voltage follower: a useful cell for low-voltage low-power circuit design”, IEEE CNF, Circuits and Systems, Volume 3, 26-29 Page(s):615 – 618, May 2002.

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