負載平衡布可夫范紐曼交換機具備很好的擴充性和100%的交換效能，已廣泛被許多著名的國際研究團隊討論，而我們組成了一個團隊去了解此一交換機架構的雛型。在這篇論文中，我們聚焦於高效率的電源系統設計來滿足所有的功能模組和電源完整性設計以限制這個交換雛型時脈顫動的影響。
首先，為了滿足兩個優先準則：安全性和可靠性，我們的電源系統包含過載熔絲保護以及熱插拔控制器。先進電信運算架構是一個瞄準在電信市場所新定義的規格，而我們採購了符合AdvancedTCA規格的標準機櫃為平台，在平台上開發我們的雛型。此機櫃提供兩路48V直流電源彼此互為備援以輸入於印刷電路板。為了操作低電壓的功能模組，如FPGA、SDRAM、以及SRAM，因此，我們套用了直流對直流轉換模組，將48V直流電壓轉換我們需求的電壓為12V、5V、3.3V、2.5V、1.8V、1.5V、1.25V以及0.75V。轉換模組設計產生需求電壓，繼承基本升壓和降壓電路。效能顯示這些轉換模組所產生的目標電壓準位在10%準確度的範圍內。此外，為了便於除錯，也設計模組隔離，以隔離在測試時的電源系統和功能模組。
穩固的電源完整性設計可以減輕時脈顫動，進一步提升系統穩定。我們提出所設計的兩種方法：印刷電路板層堆疊分配以及去耦合電容配置。交錯式電源層在印刷電路板層堆疊不僅隔離串擾的影響，而且還可以消除不必要的寄生電感所造成的電源陷落；藉由佈放去耦合電容靠近於電源汲極，當電流突然消耗時，以穩定電壓波動。

Load-balanced Birkhoff-von Neumann switch, known as scalable and theoretical 100% throughput achievable, is widely discussed in many famous international research groups, and we organized a team to realize a prototype of this switch architecture. In this paper，we focus on the efficient power subsystem design to power all the functional modules and power integrity design to restrict jitter effect of this switch prototype.
First of all, our power subsystem includes overload fuse protection and hot-swap controller to meet two priority criteria: safety and reliability. AdvancedTCA is a newly defined specification aiming at telecommunication market, and we purchased a standard AdvancedTCA chassis as a platform to build our prototype on it. This chassis provides two redundant 48VDC feeds to power the printed circuit board (PCB) inserted. To operate low voltage functional modules, such as FGPA, SDRAM, and SRAM, DC-DC conversion modules are necessary to convert 48VDC to the desired voltages: 12V, 5V, 3.3V, 2.5V, 1.8V, 1.5V, 1.25V, and 0.75V. Inheriting fundamental boost and buck circuits, conversion modules are designed to generate required voltages. Performance shows these conversion modules generate target voltage levels within 10% of accuracy. Besides, for the ease of debugging, isolation module is also designed to isolate power subsystem and functional modules during testing.
Solid power integrity design can mitigate jitter and further improve prototype stability. We address this design by two approaches: PCB layer stack allocation and decoupling capacitor deployment. Interleaving power planes in the PCB layer stack not only isolates crosstalk effect but also eliminates unwanted parasitical inductance which mainly causes power drop. Densely deploying decoupling capacitors near power drains to stabilize voltage levels upon sudden current draws.

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