近年來鐵電記憶元件在下世代記憶體元件中引起很大的注意，因為鐵電記憶元件有非揮發性，寫入讀取速度快，非破壞性讀寫，低功率消耗，單一電晶體元件等優點而成為下一世代記憶體的焦點。
在眾多鐵電記憶結構中，最被廣泛研究的結構是金屬/鐵電薄膜/絕緣層/半導體，但由於這種結構會有去極化電場(depolarization field)的影響所以導致電荷保持時間(Retention Time)過短。故本實驗是採取金屬/鐵電薄膜/複晶矽/絕緣體/半導體（MFPIS）結構，這種結構可以有效降低去極化電場的影響，進而提升記憶體元件的電荷保持時間。除此之外，本實驗還設計了三種不同的控制閘極(Control gate)-浮動閘極(Floating gate)面積比例以提供比較。絕緣體的主要目地是防止鐵電層與矽之間的交互作用，來提高元件的特性。在本實驗中成功以射頻磁控濺鍍製作金屬/鐵電薄膜/複晶矽/絕緣體/半導體（p-type）電容與電晶體，並對其電性作分析，其中鐵電薄膜是採用鋯鈦酸鉛（PZT），絕緣層則是採用氧化釔（Y2O3）薄膜。
在基本的電性量測方面，由電容-電壓的量測結果，我們得到在給予偏壓等於9伏特時來回掃描的記憶窗為2.09伏特。在電流-電壓量測結果中得到再偏壓5伏特時的漏電流為1.68×10-10 安培/平方公分。在電晶體的記憶效應方面，由IDS-VGS特性曲線的量測結果中，我們得到最大的記憶窗為2.97伏特。並且由電荷保持時間的測量中我們得到當控制閘極(Control gate)-浮動閘極(Floating gate)面積比例為0.25時所的到的效果最好：在104秒後臨限電壓(VT)還保有2.2伏特的差距。

Ferroelectric field effect transistors (FeFETs) with a metal/ferroelectric/insulator/silicon (MFIS) structure is a promising candidate for non-volatile random access memory because of its high speed, single-device structure, low power consumption, and non-destructive read-out operation. However, the FeFET memory has the problem of short retention time. The short retention time was due to the depolarization field effect and it can be fully compensated because of the high conductivity of the floating gate. A high conductive n+-polysilicon floating gate was used to reduce the depolarization field of the ferroelectric layer. In this work, we used the metal/ferroelectric/polysilicon/insulator/silicon (MFPIS) structure to overcome the short retention problem. The purpose of the insulator layer is to prevent the reaction and inter-diffusion between the ferroelectric layer and silicon layer. The Y2O3 high dielectric constant film was used as the insulator layer. It has a dielectric constant of 12~18 and good thermal stability with silicon. In this work, MFPIS capacitors and field effect transistors with the structures of Al/PZT/polysilicon/Y2O3/silicon were fabricated. These devices were used to floating gate ferroelectric random access memory (FFRAM) cells because the depolarization filed can be reduced in this structure.

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