近年來隨著各種筆記型電腦以及智慧型手機的高度需求，非揮發性記憶體(NVM)技術也跟著發展得非常快。而在記憶體元件日漸微縮的趨勢，為增加記憶體元件密度並同時優化操作特形，在本篇論文中使用可堆疊式垂直閘極快閃記憶體與無接面(Junctionless)作為元件的通道，在電荷捕捉層都為應用氮化矽和高介電係數材料的堆疊結構。在此論文主要分為三大部份去探討，(I)為了優化在三維立體結構上的熱預算問題，將會採用低溫的感應耦合電漿氣相沉積(inductively coupled plasma chemical vapor deposition, ICPCVD)去沉積穿隧氧化層、(II)在可堆疊式垂直閘極記憶體元件中，將通道做成鰭狀結構並利用其形狀的尖端效應，來改良操作特性、(III)為提高垂直堆疊元件的密度，將通道寬度微縮，再去探討不同鰭式通道寬度之間的元件操作特性。
首先，本篇論文中是在低溫的情況下，通入四氫化矽(SiH4 Silane) 與氧化亞氮(Nitrous oxide)來形成二氧化矽堆疊形成。在穿隧層上，分別使用低溫的感應耦合電漿氣相沉積(ICPCVD)所堆疊而成的穿隧氧化層(Tunneling Oxide Layer)以及使用急速升溫退火爐(KORONA)高溫快速退火氧化(Rapid Thermal Oxidation)而成的氧化層，可在實驗中得知，兩者有著差不多優良的特性。而使用ICPCVD所堆疊的穿隧氧化層(SiO2)較厚，故擁有較優的電荷保持力。使用二氧化鉿/氮化矽堆疊的電荷捕捉層比單層的氮化矽擁有較快的寫入抹除速度，在可靠度上面也有所改善，因此能帶工程對元件的特性的確有所改善。
在第二個實驗的部份，為增加可堆疊式垂直閘極快閃記憶體元件的操作特性，將會使用熱磷酸去定義出鳍狀結構的通道以達到多面閘極控制的效果。並且介由鳍狀結構的尖端來產生電場增強的效應，可以使操作速度大幅提升。在做成鰭狀結構後，也增加了多晶矽通道上電荷儲存層的面積，使得記憶窗(memory window)也提升許多。但在元件的可靠度上，由於此種立體結構在上堆疊穿隧氧化層時所使用的ICPCVD其階梯覆蓋性不佳，其堆疊出不均勻厚度的氧化層使得耐久力較差。
最後，採用不同鰭狀通道寬度的可堆疊式垂直閘極快閃記憶體元件來作元件的特性分析。通道寬度越小的元件有比較小的次臨界擺幅(S.S.)。在鰭狀通道的各個面相所堆疊出的穿隧層厚度不均勻，導致導致耐久力較差。實驗結果可得知，鰭狀通道寬度(Fin Width=15nm)的元件，即使在通道寬度從20奈米微縮至15奈米後，依然保有好的耐久力和增加可堆疊性。在未來所做高密度的可堆疊式垂直閘極快閃記憶體元件的研究可採用此寬度。

In recent years, non-volatile memory (NVM) technology is rapidly developed due to the high demands of various laptops and smartphones. Flash device should be scaled down limit to increase memory density. For improvement of operation characteristics, a vertical gate structure and Si3N4 /high-k trapping layers are applied in this dissertation. A low-temperature formed SiO2 is deposited by inductively coupled plasma chemical vapor deposition (ICPCVD). Three tasks are studied in this thesis, (I) Low-temperature formed tunneling oxide layer by ICPCVD for resolving of thermal budget issue in three dimension (3D) structure, (II) Improve operation characteristics by fin structure channel in the stacked vertical gate flash memory device, (III) Scaling down width of fin structure channel to increase density of stacked devices, and effects of fin width on operation characteristic.
In the first task, a tunneling oxide layer (SiO2) is formed by ICPCVD with Silane (SiH4) and N2O at low temperature. Operation characteristics such as program/erase (P/E) speeds, retention and endurance characteristics of device with ICPCVD formed SiO2 are as good as those with rapid thermal oxidation (RTO) formed SiO2. Device with ICPCVD formed tunneling layer has better retention characteristics due to a thicker SiO2. Compare to the device with single Si3N4, the device with HfO2/Si3N4 stacked trapping layers has faster P/E speed and good reliability characteristics truly.
In the second task, the 3D fin structure channels are formed by an orientation dependent wet etching with a phosphoric acid solution. Operation speeds of the stacked vertical gate flash memory device can be improved by the electrical field enhancement effects around the fin tip. The memory window is also increased due to more area around fin structure of poly-Si channel. However, reliability characteristics for devices of fin structure are not good because the tunneling layer thickness is not uniform cause by the poor step coverage of ICPCVD.
In last task, effects of fin structure width on stacked vertical gate flash memory device are studied. The device with smaller fin width has better subthreshold swing (S.S.), and the uniformity of its tunneling oxide layer is worse, which leads to poorer endurance characteristics. The fin width is scale-down from 20nm to 15nm which has better endurance and stacked capability. The fin width of 15 nm for this fin structure channel can be used to manufacture high-density stacked vertical gate flash memory device in the future.

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[1] K. San, C. Kaya, and T. Ma, “Effects of erase source bias on flash EPROM device reliability, ” Electron Devices, IEEE Transactions on, vol. 42, no. 1, pp. 150 –159, 1995.
[2] M. White, D. Adams, and J. Bu, “On the go with SONOS,” IEEE Circuits and Devices Magazine,, vol. 16, no. 4, pp. 22 –31, 2000.
[3] M. White, Y. Yang, A. Purwar, and M. French, “A low voltage SONOS nonvolatile semiconductor memory technology,” in Nonvolatile Memory Technology Conference, 1996., Sixth Biennial IEEE International, pp. 52 –57, 1996.
[4] J. Bu and M. White, “Retention reliability enhanced SONOS NVSM with scaled programming voltage,” in Aerospace Conference Proceedings, IEEE, vol. 5, pp. 2383–2390, 2002.
[5] K. Kahng and S. Sze, “A floating gate and its application to memory devices,” Electron Devices, IEEE Transactions on, vol. 14, no. 9, pp. 629, 1967.
[6] A. Wang and W. D. Woo, “Static magnetic storage and delay line,” Journal of Applied Physics, vol. 21, no. 1, pp. 49 –54, 1950.
[7] S. M. Sze and K. K. Ng, physics of semiconductor Devices, 3rdEd., Wiley Interscience, Hoboken, N.J. 2007.
[8] T. Y. Tseng and S. M. Sze, Eds, nonvolatile Memories Materials, Devices, and Applications, American Scientific Publishers, Stevenson Ranch, CA, 2012.
[9] N. Yamauchi, J. J. Hajjar and R. Reif, “Polysilicon thin-film transistors with channel length and width comparable to or smaller than the grain size of the thin film” IEEE Trans. Electron Devices, vol. 38, pp. 55-60, 1991.
[10] T. H. Hsu, H. T. Lue, E. K. Lai, J. Y. Hsieh, S. Y. Wang, Y. L. Wu, Y. C. King, T. Yang, K. C. Chen, K. Y. Hsieh, R. Liu and C. Y. Lu, “A high-speed BE-SONOS NAND flash utilizing the field-enhancement effect of FinFET” in IEDM Tech, pp. 913-916, 2007.
[11] R. Chau, S. Datta, M. Doczy, B. Doyle, J. Kavalieros and M. Metz, “High-k metal-gate stack and its MOSFET characteristics” Electron Devices, IEEE Transactions on, vol. 25, pp. 408-410, 2004.
[12] S. C. Lai, H. T. Lue, M. J. Yang, J. Y. Hsieh, S. Y. Wang, T. Wu, G. L. Luo, C. H. Chien, E. K. Lai, K. Y. Hsieh, R. Liu and C. Lu, “MA BE-SONOS: A bandgap engineered SONOS using metal gate and Al2O3 blocking layer to overcome erase saturation” in Non-Volatile Semiconductor Memory Workshop, pp. 88-89, 2007.
[13] Y.N.Tang,W.K.Chim, B.J.Chou, Byung, W.K.Choi, “Over-erase phenomenon in SONOS-type flash memory and its minimization using a hafnium oxide charge storage Layer” Electron Devices, IEEE Transactions on, vol. 51, pp. 1143-1147, 2004.
[14] H. T. Lue, S. Y. Wang, E. K. Lai, Y. H. Shih, S. C. Lai, L. W. Yang, K. Chen, J. Ku, K. Y. Hsieh, R. Liu and C. Y. Lu, “BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability” in IEDM Tech, pp. 547-550, 2005.
[15] Z. H. Ye, K. S. Chang-Liao, T. C. Liu, T. K. Wang, P. J. Tzeng, C. H. Lin and M. J. Tsai, “A novel SONOS-type flash device with stacked charge trapping layer” Microelectron, vol. 86, pp. 1863-1865, 2009.
[16] J. P. Colinge, I. Ferain, A. Kranti, C. W. Lee, N. D. Akhavan, P. Razavi, R. Yan and R. Yu, “Junctionless nanowire transistor: complementary metal-oxide-semiconductor without junctions” vol. 3, pp. 477-482, 2011.
[17] J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O'Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy and R. Murphy, “Nanowire transistors without junctions” Nat, Nanotechnol, vol. 5, pp. 225-229, 2010.
[18] C. J. Su, T. K. Su, T. I. Tsai, H. C. Lin and T. Y. Huang, “A junctionless SONOS nonvolatile memory device constructed with in situ-doped polycrystalline silicon nanowires” Nanoscale Res, Lett, vol. 7, pp. 1-6, 2012.
[19] H. T. Lue, Y. H. Hsiao, P. Y. Du, S. C. Lai, T. H. Hsu, S. P. Hong, M. T. Wu, F. H. Hsu, N. Z. Lien, C. P. Lu, J. Y. Hsieh, L. W. Yang, T. Yang, K. C. Chen, K. Y. Hsieh, R. Liu and C. Y. Lu, “A novel buried-channel FinFET BE-SONOS NAND flash with improved memory window and cycling endurance” in VLSI Symp, Tech, pp. 224-225, 2009.
[20] R. Katsumata, M. Kito, Y. Fukuzumi, M. Kido, H. Tanaka, Y. Komori, M. Ishiduki, J. Matsunami, T. Fujiwara, Y. Nagata, Li Zhang, Y. Iwata, R. Kirisawa, H. Aochi and A. Nitayama, “Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices” in VLSI Symp, Tech, pp. 136-137, 2009,.
[21] J. Jang, H. S. Kim, W. Cho, H. Cho, J. Kim, S. I. Shim, Y. Jang, J. H. Jeong, B. K. Son, D. W. Kim, J. J. Shim, J. S. Lim, K. H. Kim, S. Y. Yi, J. Y. Lim, C. Dewill, H. C. Moon, S. Hwang, J. W. Lee, Y. H. Son, U. Chung and W. S. Lee, “Vertical cell array using TCAT(terabit cell array transistor) technology for ultra high density NAND flash memory” in VLSI Symp. Tech, pp. 192-193, 2009.
[22] W. Tsai, N. Zous, C. Liu, C. Liu, C. Chen, T. Wang, S. Pan, C.-Y. Lu, and S. Gu, “Data retention behavior of a SONOS type two-bit storage flash memory cell” in Electron Devices Meeting, IEDM, Technical Digest, International, pp. 32.6.1 –32.6.4, 2001.
[23] Z. H. Ye, K. S. Chang-Liao, C. Y. Tsai, T. T. Tsai and T. K. Wang, “Enhanced Operation in Charge-Trapping Nonvolatile Memory Device With Si3N4/Al2O3/HfO2 Charge-Trapping Layer” IEEE Electron Device Lett, vol. 33, pp. 1351-1353, 2012.
[24] T. Yan-Ny, W. K. Chim, C. Wee Kiong, J. Moon-Sig, and B. Jin Cho, “Hafnium aluminum oxide as charge storage and blocking-oxide layers in SONOS-type nonvolatile memory for high-speed operation” Electron Devices, IEEE Transactions on, vol. 53, pp. 654-662, 2006.
[25] M. Heyns, S. Beckx, H. Bender, P. Blomme, W. Boullart, B. Brijs, et al., “Scaling of high-k dielectrics towards sub-1nm EOT” in VLSI Technology, Systems, and Applications, International Symposium on, pp. 247-250, 2003.
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