在數位訊號處理系統中，乘法器扮演著極其重要的角色。然而在有些數位訊號處理系統的應用中，乘法器的輸入與輸出需為相同長度的位元數，如此一來必須捨棄n位元的輸出(固定位元式乘法器)，會影響到乘法器的準確度，因此，很多人開始致力於研究如何提高乘法器的精確度。
本篇論文分別提出一個高精確度的陣列乘法器與一個可彈性應用於高位元的Booth乘法器。在陣列乘法器的應用中，我們以統計學的方式分別於不同長度的乘法器執行模擬，可得到一通式去估算捨去的部分，以一個0.18μm的八位元陣列乘法器為例，本文所提出方法之精確度相較於Direct-T乘法器高出15.65%，又與Post-T乘法器比較可省下41%的面積，僅以低面積的條件達到高精確度的固定位元式乘法器。
本文所提出的Booth乘法器則是先將部份乘積做一些轉換，並利用機率期望值的概念做一些數學運算，如此一來，我們可以得到一個計算補償值的通式及一個簡單的電路架構，即便在高位元的應用中，也可輕易的以手算方式得到我們想要的補償值，相較於其他已提出的補償方法，可節省大量複雜的模擬所需花費的時間。為了證明此乘法器在實際應用中的效益，我們直接將它用於一個DCT的應用中，結果顯示其可省下23%的面積但只損失4dB的PSNR值。

Multiplier is an important component in the application of digital signal processing (DSP) systems. However, it is desirable to remain the same bit width for the multiplication in some applications. For this reason, fixed-width multipliers only keeps the most significant half part of the products and a large error would be produced. Thus, many compensation methods are provided to solve this problem.
In this research, an error compensation method for fixed-width two’s-complement array multipliers is proposed at first. According to the statistical analysis for the truncation term, a general form for different word width compensation circuit is made up. For the 8×8 fixed-width multiplier as an example, the proposed method achieve 15:65% accuracy comparison with Direct-t method. Also, the proposed multiplier has 41% savings in gate count comparison with post-truncation multiplier when it is implemented in a 0:18-um process. Therefore, the proposed multiplier has a low hardware cost achieving high accuracy designs.
Then, a probabilistic estimation compensation (PEC) method for fixed-width Booth multiplier is presented. According to the probabilistic analysis for the truncation part, we
can obtain a formula to calculate the compensation value easily. In the application of long bit width, we can not only avoid the exhaustive simulation but also implement in a simple compensation circuit architecture with nice accuracy. Compared to the previous works, the proposed method achieve better performance. In order to verify the performance of PEC multipliers in real applications, an 8 × 8 two-dimensional (2-D) discrete cosine transform (DCT) is implemented in a 0:18-um process. The result shows that the proposed PEC method can save 23% area with 4dB peak signal-to-noise ratio (PSNR) penalty.

[1] B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs. New York: Oxford Univ. Press, 1999.
[2] A. D. Booth, “ A Signed Binary Multiplication Technique, ” Quart. J. Mech. Appl. Math., vol. 4, part2, pp. 236-240, 1951.
[3] Y. Wang, J. Ostermann, and Y. Q. Zhang, Video processing and Communications, Upper Saddle River, New Jersey: Prentice Hall, 2002.
[4] C. R. Baugh and B. A. Wooley, “ A Two’s Complement Parallel Array Multiplication Algorithm, ” IEEE Trans. Computers, vol. C-22, no. 12, pp. 1045-1047, Dec. 1973.
[5] D. P. Agrawal and T. R. N. RAO, “ On Multiple Operand Addition of Signed Binary Numbers, ” IEEE Trans. Computers, vol. 27, pp. 1068-1070, Nov. 1978.
[6] Y. C. Lin, “ Single-Precision Multiplier with Reduced Circuit Complexity for Signal Processing Application, ” IEEE Trans. Computers, vol. 41, no. 10, pp. 1333-1336,
Oct. 1992.
[7] M. J. Schulte and E. E. Swartzlander Jr., “ Truncated Multiplication with Correction Constant, ” VLSI Signal Process VI, vol. 6, pp. 388-396, Oct. 1993.
[8] S. S. Kidambi, F. El-Guibaly, and A. Antonious, “ Area-Efficient Multipliers for Digital Signal Processing Applications, ” IEEE Trans. Circuits Syst. II, Anal. Digit.
Signal Process, vol. 43, no. 2, pp. 90-95, Feb. 1996.
[9] E. J. King and E. E. Swartzlander Jr., “ Data-Dependent Truncation Scheme for Parallel Multipliers, ” in Proc. 31th Asilomar Conf. on Signals, Circuits Syst., vol. 2, Nov. 1997, pp. 1178-1182.
[10] J. M. Jou and S. R. Kuang, “ Design of Low-Error Fixed-Width Multipliers for DSP Applications, ” Electron lett., vol. 33, no. 19, pp. 1597-1598, Jun. 1997.
[11] J. M. Jou, S. R. Kuang, and R. D. Chen, “ Design of Low-Error Fixed-Width Multipliers for DSP Applications, ” IEEE Trans. Circuits Syst. II, vol. 46, no. 6, pp. 836-842, Jun. 1999.
[12] E. E. Swartzlander Jr., “ Truncated Multiplication with Approximate Rounding, ” in Proc. 33rd Asilomar Conf. Signals, Systems, and Computers, vol. 2, 1999, pp.
1480-1483.
[13] L. D. Van, S. S. Wang, S. Tengchen, W. S. Feng, and B. S. Jeng, “ Design of a lower-error fixed-width multiplier for speech processing application, ” in Proc. IEEE
Int. Symp. Circuits and Systems, vol. 3, May 1999, pp. 130-133.
[14] S. J. Jou and H. H. Wang, “ Fixed-Width Multiplier for DSP Application, ” in Proc. International Conf. Computer Design (ICCD), Sep. 2000, pp. 318-322.
[15] L. D. Van, S. S. Wang, and W. S. Feng, “ Design of the Lower Error Fixed-Width Multiplier and Its Application, ” IEEE Trans. Circuits Syst. II, vol. 47, no. 10, pp.
1112-1118, Oct. 2000.
[16] L. D. Van and C. C. Yang, “ Generalized Low-Error Area-Efficient Fixed-Width Multipliers, ” IEEE Trans. Circuits Syst. I, vol. 52, no. 8, pp. 1608-1619, Aug. 2005.
[17] T. B. Juang and S. F. Hsiao, “ Low-Error Carry-Free Fixed-Width Multipliers with Low-Cost Compensation Circuits, ” IEEE Trans. Circuits Syst. II, vol. 52, no. 6, pp. 299-303, Jun. 2005
[18] Y. C. Liao, H. C. Chang, and C. W. Liu, “ Carry Estimation for Two’s Complement Fixed-Width Multipliers, ” in Workshop on Signal Process Syst. (SiPS), Banff,
Canada, Oct. 2006, pp. 345-350.
[19] V. Garofalo, N. Petra, D. D. Caro, A. G. M. Strollo, and E. Napoli, “ Low Error Truncated Multipliers for DSP Applications, ” in proc. IEEE Conf. on Electronics,
Circuits and Systems, Aug. 2008, pp. 29-32.
[20] N. Petra, D. D. Caro, V. Garofalo, E. Napoli, and A. G. M. Strollo, “ Truncated Binary Multipliers with Variable Correction and Minimum Mean Square Error, ”
IEEE Trans. Circuits Syst. I, vol.57, no. 6, pp.1312-1325, Jun. 2010.
[21] S. J. Jou, M. H. Tsai, and Y. L. Tsao, “ Low-Error Reduced-Width Booth Multipliers for DSP Applications, ” IEEE Trans. Circuits Syst. I, vol. 50, no. 11, pp. 1470-1474, Nov. 2003.
[22] K. J. Cho, K. C. Lee, J. G. Chung, and K. K. Parhi, “ Design of Low-Error Fixed-Width Modified Booth Multiplier, ” IEEE Trans. VLSI Systems, vol. 12, no. 5, pp. 522-531, May 2004.
[23] H. A. Huang, Y. C. Liao, and H. C. Chang, “ A Self-Compensation Fixed-Width Booth Multiplier and Its 128-Point FFT Applications, ” in Proc. IEEE Int. Symp.
Circuits and Syst. (ISCAS), 2006, pp. 3358-3541.
[24] M. A. Song, L. D. Van, and S. Y. Kuo, “ Adaptive Low-Error Fixed-Width Booth Multipliers, ” IEEE Trans. Fundamentals, vol. E90-A, no. 6, pp. 1180-1187, Jun. 2007.
[25] K. K. Parhi, J. G. Chung, and K. C. Lee “ Low-Error Fixed-Width Modified Booth Multiplier, ” United States Patent 7334200, 2008.
[26] J. P. Wang, S. R. Kuang, and S. C. Liang, “ High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications, ” IEEE Trans. VLSI Systems, vol. 19, no. 1, pp. 52-60, Jan. 2011.
[27] C. Y. Li, Y. H. Chen, T. Y. Chang, and J. N. Chen, “ A Probabilistic Estimation Bias Circuit for Fixed-Width Booth Multiplier and Its DCT Applications, ” IEEE
Trans. Circuits and Systems II, vol. 58, no. 4, pp. 215-219, April 2011.
[28] Y. H. Chen, T. Y. Chang, and R. Y. Jou, “ A Statistical Error-Compensated Booth Multipliers and Its DCT Application, ” in proc. IEEE Conf. on Tencon, Nov. 2011,
pp. 1146-1149.
[29] M. J. Schulte, J. E. Stine, and J. G. Jansen, “ Reduced Power Dissipation through Truncated Multiplication, ” in Proc. IEEE Alessandro Volta Memorial Workshop on
Low-Power Design, Mar. 1999, pp. 61-69.
[30] A. G. M. Strollo, N. Petra, and D. De Caro, “ Dual-Tree Error Compensation for High Performance Fixed-Width Multipliers, ” IEEE Trans. Circuits Syst. II: Express Briefs, vol. 52, no. 8, pp. 501-507, Aug. 2005.
[31] J. Y. Kang and J. L. Gaudiot, “ A Simple High-Speed Multiplier Design, ” IEEE Trans on Computers, vol. 55, no. 10, pp. 1253-1258, Oct. 2006.
[32] E. de. Angel and. E. E. Swartzlander Jr., “ Low Power Parallel Multipliers, ” in Workshop VLSI Signal Process. IX, 1996, pp. 199-208.
[33] A. A. Farooqui and V. G. Oklobdzija, “ General Data-Path Organization of A MAC Unit for VLSI Implemetation of DSP Processors, ” in IEEE Int. Symp.Circuits Syst.,
vol. 2, 1998, pp. 260-263.
[34] K. Choi and M. Song, “ Design of A High Performance 32 × 32-bit Multiplier with A Novel Sign Select Booth Encoder, ” in Proc. IEEE Int. Symp.Circuits Syst., vol.
2, 2001, pp. 701-704.
[35] S. C. Hsia and S. H. Wang, “ Shift-Register-Based Data Transposition for Cost-Effective Discrete Cosine Transform, ” IEEE Trans. VLSI Systems, vol. 15, no. 6,
pp. 725-728, Jun. 2007.