鐵電氧化鉿鋯與多層堆疊矽與鍺於鰭式與環繞式閘極電晶體之研究

簡易檢索 / 詳目顯示

回結果列表

研究生：	蔡孟儒 Tsai, Meng-Ju
論文名稱：	鐵電氧化鉿鋯與多層堆疊矽與鍺於鰭式與環繞式閘極電晶體之研究 Study of Ferroelectric HfZrO and Multi-stacked Silicon and Germanium on Fin and Gate-all-around Field-effect Transistors
指導教授：	吳永俊 Wu, Yung-Chun
口試委員:	巫勇賢 Wu, Yung-Hsien 林育賢 Lin, Yu-Hsien 蘇俊榮 Su, Chun-Jung 侯福居 Hou, Fu-Ju
學位類別：	博士 Doctor
系所名稱：	原子科學院 - 工程與系統科學系 Department of Engineering and System Science
論文出版年：	2020
畢業學年度：	108
語文別：	英文
論文頁數：	152
中文關鍵詞：	無接面式電晶體、奈米薄片、鰭式場效電晶體、環繞式閘極場效電晶體、氧化鉿鋯、鐵電、次臨界擺幅、負電容
外文關鍵詞：	Junctionless field effect transistor (JLFET), Nanosheet (NS), Fin field effect transistor (FinFET), Gate-all-around field effect transistor (GAAFET), Hafnium zirconium oxide (HfZrO), Ferroelectric, Subthreshold swing (SS), Negative capacitance (NC)
相關次數：	點閱：2 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

因應市場需求，電子產品不僅要追求高速、高效能，必須兼備低耗電與低成本。現今全球各大半導體廠面對元件持續的微縮，製程技術或達到良好元件性能的困難度，已隨之上升，單純地縮減通道長度，或將介電層厚度持續降低，已無法得到良好的電流開關比、高電流驅動力、低漏電和極佳可靠度的需求，開發出一個滿足高性能與可擴展性的目標相當重要。因此本論文主要將應用於後莫爾定律時代之延伸，探討反轉式與無接面式通道多閘極電晶體，並結合鐵電閘極氧化層之研究，以符合未來電晶體技術的可能性。本論文共分為三個部份，(1)超薄奈米薄片混和通道無接面式場效電晶體，(2)堆疊式奈米薄片通道之多閘極場效電晶體，(3)鐵電閘極氧化層應用於先進結構場效電晶體。
第一部份主要以奈米薄片通道無接面式電晶體。首先提出奈米薄片無接面式電晶體搭配混合式反參雜通道，藉由不同型參雜之結構設計，產生空乏區，使通道等效厚度變薄，以獲得較佳的關閉特性。更進一步提出，利用相同光罩但不同的曝光劑量，可以得到不同線寬的通道，並製作出不同結構的堆疊奈米薄片電晶體。
第二部份提出，以堆疊式奈米薄片通道的無接面式場效電晶體，比較其多閘極與環繞式閘極結構之特性，進一步利用三維半導體元件模擬技術，模擬堆疊奈米薄片無接面式電晶體比較不同閘極結構之特性，進一步探討閘極微縮以及通道尺寸的特性影響。
第三部份提出，小於五奈米之鐵電層氧化鉿鋯結合鰭式與環繞式閘極電晶體。首先提出利用同步輻射光與奈米繞射點分析小於五奈米以下之鐵電薄膜，驗證其晶體結構。接著將小於五奈米之鐵電層氧化鉿鋯應用於先進結構之電晶體當中，探討暫態負電容效應。不同於一般閘極氧化層的結果，可以得到次臨界擺幅(SS)低於60mV/decade、較低之汲極引發位能障下降(DIBL)以及較高之開電流等優越性能。

In response to market demand, electronic products not only need to pursue high speed and high efficiency, and must have both low power consumption and low cost. Nowadays, the major semiconductor factories in the world are facing continuous miniaturization of components, and the difficulty of process technology or achieving good device performance has risen. Simply reducing the channel length or keeping the thickness of the dielectric layer continuously decreasing has been unable to obtain a good electrical switching ratio, high on/off current ratio, high driving power, low current leakage, and excellent reliability. It is very important to develop a goal to meet high performance and scalability. Therefore, this paper will mainly be applied to the extension of the post-Moore's Law era, to explore the inversion and junctionless channel multi-gate transistors combined with the research of ferroelectric gate oxide layer to meet the possibility of future transistor technology. This thesis is divided into three parts, (1) ultra-thin nanosheet (NS) hybrid channel junctionless field effect transistor (JLFET), (2) stacked nanosheet channel multi-gate field effect transistor, (3) ferroelectric gate oxide layer is used in field effect transistors with advanced structure.
The first part is mainly based on the nanosheet channel junctionless transistor. First of all, it is proposed that the nanosheet junctionless transistors are equipped with hybrid anti-doped channels. Through the design of the different doping structure, an extra depletion region is created, and the equivalent thickness of the channel is thinned to obtain better depleted characteristics. It is further proposed that using the same mask but different exposure doses, channels with different line widths can be obtained, and stacked nanosheet transistors with different structures can be fabricated.
The second part proposes the use of stacked nanosheet channel junctionless field-effect transistors to compare the characteristics of its multi-gate and gate-all-around structure, and further uses 3D TCAD to simulate junctionless stacked nanosheets comparing the characteristics of different gate structures, and discussing the influence of gate scaling down and channel size characteristics.
The third part proposes a ferroelectric layer of less than 5 nm of hafnium zirconium oxide combined with fin field effect transistor (FinFET) and gate-all-around field effect transistor (GAAFET). Firstly, the use of synchrotron radiation and nano-beam diffraction to analyze ferroelectric thin films less than 5 nm to verify their crystal structure. Then the hafnium zirconium oxide (HfZrO) ferroelectric layer less than 5 nm is used in the advanced structure of the transistor to discuss the transient negative capacitance (NC) effect. Different from the results of general gate oxide layer, superior performance such as subthreshold swing (SS) below 60mV/decade, lower drain-induced barrier lowering (DIBL) and higher on-current can be obtained.

中  文  摘  要    i
Abstract    iii
Acknowledge    vi
Contents    viii
List of Figures    xii
Chapter 1  Introduction    1
1-1    Challenges of Device Scaling and Opportunities    1
1-2    Junctionless Field-Effect Transistor    3
1-2.1     Superiority of Junctionless Transistor    3
1-2.2     Basic Principle of Junctionless Transistor    5
1-2.3     Threshold voltage of Junctionless Transistor    10
1-3    Introduction of 3D device    13
1-3.1  Multi-Gate Field-Effect Transistor    13
1-3.2  Stacked Gate–all-around Field-Effect Transistor    17
1-5  High mobility channel materials    20
1-5.1  Germanium based field effect transistor    22
1-6  References    26
Chapter 2  Ferroelectric FET Theory    33
2-1     Ferroelectric and Negative Capacitance(NC) FET    33
2-2     Landau-Khalatnikov (L-K) equation    39
2-3     Development of NC Theory    41
2-4     Fabrication and structure of NCFET    49
2-5     Reference    53
Chapter 3  Hybrid N-type Poly-Si Ultra-Thin Nanowire Shell Channel with P-substrate Structure by Electron Beam Lithography Adjustment for Junctionless Field-Effect Transistors    56
3-1    Motivation and Literature Review    56
3-2    Device Fabrication    58
3-3    Results and Discussion    61
3-4    Summary    69
3-5    References    70
Chapter 4  Fabrication and Characterization of Stacked Poly-Si Nanosheet with Gate-all-around and Multi-gate Junctionless Field Effect Transistors    74
4-1    Motivation and Literature Review    74
4-2    Device Fabrication    76
4-3    Results and Discussion    78
4-3.1     Tri-gate and Omega-gate    78
4-3.2     Gate-all-around    86
4-4    TCAD simulation    91
4-5    Summary    93
4-6    References    94
Chapter 5  Atomic-level Analysis of sub-5 nm-thick Hf0.5Zr0.5O2 and Characterization of Nearly Hysteresis-free Ferroelectric FinFET    98
5-1    Motivation and Literature Review    98
5-2　   Device Fabrication    99
5-3　   Results and Discussion    99
5-4　   Summary    108
5-5     References    109
Chapter 6  Investigation of 5-nm-thick Hf0.5Zr0.5O2 Ferroelectric FinFET Dimensions for sub-60-mV/decade Subthreshold Slope    113
6-1    Motivation and Literature Review    113
6-2　   Device Fabrication    114
6-3　   Results and Discussion    115
6-4　   Summary    122
6-5     References    123
Chapter 7  Germanium Nanowire Ferroelectric HfZrO Junctionless Gate-all-around FETs with Steep Subthreshold Slope    128
7-1    Motivation and Literature Review    128
7-2　   Device Fabrication    129
7-3　   Results and Discussion    130
7-4　   Summary    136
7-5     References    137
Chapter 8  Conclusion    142
Curriculum Vitae    144
Publication List    145
Appendix    149


                                

[1] H. H. Radamson, Y. Zhang, X. He, H. Cui, J. Li, J. Xiang, J. Liu, S. Gu, and G. Wang, "The Challenges of Advanced CMOS Process from 2D to 3D," Applied Sciences, vol. 7, 2017. doi:10.3390/app7101047.
[2] N. Horiguchi, "CMOS Device Architecture Evolution and Metrology Challenges," in 2018 Workshop on Characterization and Metrology for 3D CMOS, 2018.
[3] International Roadmap for Devices and Systems (IRDS™) 2017 Edition. [Online]. Available: https://irds.ieee.org/roadmap-2017
[4] Zsolt Tőkei, " Sub-5nm Interconnect Trends and Opportunities," in 2017 IEEE International Electron Devices Meeting, 2017, Short Course 1: Boosting Performance, Ensuring Reliability, Managing Variation in sub-5nm CMOS.
[5] J.-P. Colinge, C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, et al., "Nanowire transistors without junctions," Nature Nanotechnology, vol. 5, p. 225, 02/21/online 2010.
[6] C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and J.-P. Colinge, "Junctionless multigate field-effect transistor," Applied Physics Letters, vol. 94, p. 053511, 2009/02/02 2009.
[7] E. Gnani, A. Gnudi, S. Reggiani, and G. Baccarani, "Theory of the junctionless nanowire FET," IEEE Transactions on Electron Devices, vol. 58, pp. 2903-2910, 2011.
[8] P. Razavi, G. Fagas, I. Ferain, R. Yu, S. Das, and J.-P. Colinge, "Influence of channel material properties on performance of nanowire transistors," Journal of Applied Physics, vol. 111, p. 124509, 2012/06/15 2012.
[9] C. W. L. J. P. Colinge, N. Dehdashti Akhavan, R. Yan, I. Ferain, P. Razavi, A. Kranti, and R. Yu, "Junctionless Transistors: Physics and Properties," in Semiconductor-On-Insulator Materials for Nanoelectronics Applications, F. B. Alexei Nazarov, Francisco Gamiz, J.-P. Colinge, Jean-Pierre Raskin, V.S. Lysenko, Ed., ed: SPRINGER, 2011.
[10] R. Yan, A. Kranti, I. Ferain, C.-W. Lee, R. Yu, N. Dehdashti, et al., "Investigation of high-performance sub-50nm junctionless nanowire transistors," Microelectronics Reliability, vol. 51, pp. 1166-1171, 2011/07/01/ 2011.
[11] J. P.Colinge, FinFETs and Other Multi-Gate Transistors: Springer, 2008.
[12] S. D. Kim, M. Guillorn, I. Lauer, P. Oldiges, T. Hook, and M. H. Na, "Performance Trade-offs in FinFET and Gate-All Around Device Architectures for 7nm-node and Beyond," 2015 Ieee Soi-3d-Subthreshold Microelectronics Technology Unified Conference (S3s), 2015.
[13] N. Loubet, T. Hook, P. Montanini, C. W. Yeung, S. Kanakasabapathy, M. Guillom, et al., "Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET," in 2017 Symposium on VLSI Technology, 2017, pp. T230-T231.
[14] S. Natarajan, M. Agostinelli, S. Akbar, M. Bost, A. Bowonder, V. Chikarmane, S. Chouksey, A. Dasgupta, K. Fischer, Q. Fu, T. Ghani, M. Giles, S. Govindaraju, R. Grover, W. Han, D. Hanken, E. Haralson, M. Haran, M. Heckscher, R. Heussner, P. Jain, R. James, R. Jhaveri, I. Jin, H. Kam, E. Karl, C. Kenyon, M. Liu, Y. Luo, R. Mehandru, S. Morarka, L. Neiberg, P. Packan, A. Paliwal, C. Parker, P. Patel, R. Patel, C. Pelto, L. Pipes, P. Plekhanov, M. Prince, S. Rajamani, J. Sandford, B. Sell, S. Sivakumar, P. Smith, B. Song, K. Tone, T. Troeger, J. Wiedemer, M. Yang, and K. Zhang, " A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2SRAM cell size," in 2014 IEEE International Electron Devices Meeting, 2014, pp. 3.7.1-3.7.3. doi:10.1109/IEDM.2014.7046976.
[15] M. G. Bardon, Y. Sherazi, D. Jang, D. Yakimets, P. Schuddinck, R. Baert, H. Mertens, L. Mattii, B. Parvais, A. Mocuta, and D. Verkest, "Power-performance Trade-offs for Lateral NanoSheets on Ultra-Scaled Standard Cells," in 2018 IEEE Symposium on VLSI Technology, 2018, pp. 143-144. doi:10.1109/VLSIT.2018.8510633.
[16] S. Barraud, V. Lapras, B. Previtali, M. P. Samson, J. Lacord, S. Martinie, M. Jaud, S. Athanasiou, F. Triozon, O. Rozeau, J. M. Hartmann, C. Vizioz, C. Comboroure, F. Andrieu, J. C. Barbé, M. Vinet, and T. Ernst, "Performance and design considerations for gate-all-around stacked-NanoWires FETs," in 2017 IEEE International Electron Devices Meeting (IEDM), 2017, pp. 29.2.1-29.2.4. doi:10.1109/IEDM.2017.8268473.
[17] L. Cai, W. Chen, G. Du, X. Zhang, and X. Liu, "Layout Design Correlated With Self-Heating Effect in Stacked Nanosheet Transistors," IEEE Transactions on Electron Devices, vol. 65, pp. 2647-2653 2018. doi:10.1109/TED.2018.2825498.
[18] N. Loubet, T. Hook, P. Montanini, C. Yeung, S. Kanakasabapathy, M. Guillom, T. Yamashita, J. Zhang, X. Miao, J. Wang, A. Young, R. Chao, M. Kang, Z. Liu, S. Fan, B. Hamieh, S. Sieg, Y. Mignot, W. Xu, S. Seo, J. Yoo, S. Mochizuki, M. Sankarapandian, O. Kwon, A. Carr, A. Greene, Y. Park, J. Frougier, R. Galatage, R. Bao, J. Shearer, R. Conti, H. Song, D. Lee, D. Kong, Y. Xu, A. Arceo, Z. Bi, P. Xu, R. Muthinti, J. Li, R. Wong, D. Brown, P. Oldiges, R. Robison, J. Arnold, N. Felix, S. Skordas, J. Gaudiello, T. Standaert, H. Jagannathan, D. Corliss, M. Na, A. Knorr, T. Wu, D. Gupta, S. Lian, R. Divakaruni, T. Gow, C. Labelle, S. Lee, V. Paruchuri, H. Bu, and M. Khare, "Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET," in 2017 Symposium on VLSI Technology, 2017, pp. T230-T231. doi:10.23919/VLSIT.2017.7998183.
[19] B.-H. Lee, M.-H. Kang, D.-C. Ahn, J.-Y. Park, T. Bang, S.-B. Jeon, J. Hur, D. Lee, and Y.-K. Choi, "Vertically Integrated Multiple Nanowire Field Effect Transistor," Nano Letters, vol. 15, pp. 8056-8061, 2015. doi:10.1021/acs.nanolett.5b03460.
[20] ARM® core processor [http://www.arm.com].
[21] M. Kobayashi, "A perspective on steep-subthreshold-slope negative-capacitance field-effect transistor," Applied Physics Express, vol. 11, no. 11, p. 110101, 2018.
[22] E. Ko, J. Shin, and C. Shin, "Steep switching devices for low power applications: negative differential capacitance/resistance field effect transistors," Nano Convergence, vol. 5, pp. 2, 2018. doi:10.1186/s40580-018-0135-4.
[23] S. Salahuddin and S. Datta, "Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices," Nano Letters, vol. 8, pp. 405-410, 2008. doi:10.1021/nl071804g.
[24] T. Mikolajick, et al., "Basics and Device Applications of Ferroelectricity in Hafnium Oxides,“ namlab.
[25] A. I. Khan, K. Chatterjee, B. Wang, S. Drapcho, L. You, C. Serrao, S. R. Bakaul, R. Ramesh, and S. Salahuddin, "Negative capacitance in a ferroelectric capacitor," Nature Materials, vol. 14, no. 2, pp. 182-186, 2015/02/01 2015, doi: 10.1038/nmat4148..
[26] Z. Liu, M. A. Bhuiyan, and T. P. Ma, "A Critical Examination of ‘Quasi-Static Negative Capacitance’ (QSNC) theory," in 2018 IEEE International Electron Devices Meeting (IEDM), 1-5 Dec. 2018 2018, pp. 31.2.1-31.2.4, doi: 10.1109/IEDM.2018.8614614.
[27] M. N. K. Alam, P. Roussel, M. Heyns, and J. Van Houdt, "Positive non-linear capacitance: the origin of the steep subthreshold-slope in ferroelectric FETs," Scientific Reports, vol. 9, no. 1, p. 14957, 2019/10/18 2019, doi: 10.1038/s41598-019-51237-2.
[28] E. Ko, H. Lee, Y. Goh, S. Jeon, and C. Shin, "Sub-60-mV/decade Negative Capacitance FinFET With Sub-10-nm Hafnium-Based Ferroelectric Capacitor," IEEE Journal of the Electron Devices Society, vol. 5, pp. 306-309, 2017. doi:10.1109/JEDS.2017.2731401.
[29] E. Ko, J. W. Lee, and C. Shin, "Negative Capacitance FinFET With Sub-20-mV/decade Subthreshold Slope and Minimal Hysteresis of 0.48 V," IEEE Electron Device Letters, vol. 38, pp. 418-421, 2017. doi:10.1109/LED.2017.2672967.
[30] K.-S. Li, P.-G. Chen, T.-Y. Lai, C.-H. Lin, C.-C. Cheng, C.-C. Chen, Y.-J. Wei, Y.-F. Hou, M.-H. Liao, M.-H. Lee, M.-C. Chen, J.-M. Sheih, W.-K. Yeh, F.-L. Yang, S. Salahuddin, and C. Hu, "Sub-60mV-swing negative-capacitance FinFET without hysteresis," in 2015 IEEE International Electron Devices Meeting (IEDM), 2015, pp. 22.6.1-22.6.4. doi:10.1109/IEDM.2015.7409760.
[31] M. H. Lee, S. Fan, C. Tang, P. Chen, Y. Chou, H. Chen, J. Kuo, M. Xie, S. Liu, M. Liao, C. Jong, K. Li, M. Chen, and C. W. Liu, "Physical thickness 1.x nm ferroelectric HfZrOx negative capacitance FETs," in 2016 IEEE International Electron Devices Meeting (IEDM), 2016, pp. 12.1.1-12.1.4. doi:10.1109/IEDM.2016.7838400.
[32] M. H. Lee, P.-G. Chen, S.-T. Fan, C.-Y. Kuo, H.-H. Chen, S.-S. Gu, Y.-C. Chou, C.-H. Tang, R.-C. Hong, Z.-Y. Wang, M.-H. Liao, K.-S. Li, M.-C. Chen, and C. W. Liu, "Negative capacitance FETs with steep switching by ferroelectric Hf-based oxide," in 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2017, pp. 1-2. doi:10.1109/VLSI-TSA.2017.7942466.
[33] D. Kwon, K. Chatterjee, A. J. Tan, A. K. Yadav, H. Zhou, A. B. Sachid, R. d. Reis, C. Hu, and S. Salahuddin, "Improved Subthreshold Swing and Short Channel Effect in FDSOI n-Channel Negative Capacitance Field Effect Transistors," IEEE Electron Device Letters, vol. 39, pp. 300-303, 2018. doi:10.1109/LED.2017.2787063.
[34] A. K. Yadav, K. X. Nguyen, Z. Hong, P. García-Fernández, P. Aguado-Puente, C. T. Nelson, S. Das, B. Prasad, D. Kwon, S. Cheema, A. I. Khan, C. Hu, J. Íñiguez, J. Junquera, L.-Q. Chen, D. A. Muller, R. Ramesh, and S. Salahuddin, "Spatially resolved steady-state negative capacitance," Nature, vol. 565, pp. 468-471, 2019. doi:10.1038/s41586-018-0855-y.
[35] C. H. Cheng and A. Chin, "Low-Voltage Steep Turn-On pMOSFET Using Ferroelectric High-<formula formulatype="inline"> <tex Notation="TeX">$\kappa$</tex></formula> Gate Dielectric," IEEE Electron Device Letters, vol. 35, pp. 274-276, 2014. doi:10.1109/LED.2013.2291560.
[36] R. Pillarisetty, "Academic and industry research progress in germanium nanodevices," Nature, vol. 479, no. 7373, pp. 324-328, 2011/11/01 2011, doi: 10.1038/nature10678.
[37] S. Takagi et al., "Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance," IEEE Transactions on Electron Devices, vol. 55, no. 1, pp. 21-39, 2008.
[38] C. Chung, C. Chen, J. Lin, C. Wu, C. Chien, and G. Luo, "First experimental Ge CMOS FinFETs directly on SOI substrate," in 2012 International Electron Devices Meeting, 2012, pp. 16.4.1-16.4.4.
[39] P. Goley and M. K. Hudait, Germanium Based Field-Effect Transistors: Challenges and Opportunities. 2014.
[40] ARM® core processor [http://www.arm.com].
[41] M. Kobayashi, "A perspective on steep-subthreshold-slope negative-capacitance field-effect transistor," Applied Physics Express, vol. 11, no. 11, p. 110101, 2018.
[42] E. Ko, J. Shin, and C. Shin, "Steep switching devices for low power applications: negative differential capacitance/resistance field effect transistors," Nano Convergence, vol. 5, pp. 2, 2018. doi:10.1186/s40580-018-0135-4.
[43] S. Salahuddin and S. Datta, "Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices," Nano Letters, vol. 8, pp. 405-410, 2008. doi:10.1021/nl071804g.
[44] T. Mikolajick, et al., "Basics and Device Applications of Ferroelectricity in Hafnium Oxides,“ namlab.
[45] A. I. Khan, K. Chatterjee, B. Wang, S. Drapcho, L. You, C. Serrao, S. R. Bakaul, R. Ramesh, and S. Salahuddin, "Negative capacitance in a ferroelectric capacitor," Nature Materials, vol. 14, no. 2, pp. 182-186, 2015/02/01 2015, doi: 10.1038/nmat4148..
[46] Z. Liu, M. A. Bhuiyan, and T. P. Ma, "A Critical Examination of ‘Quasi-Static Negative Capacitance’ (QSNC) theory," in 2018 IEEE International Electron Devices Meeting (IEDM), 1-5 Dec. 2018 2018, pp. 31.2.1-31.2.4, doi: 10.1109/IEDM.2018.8614614.
[47] M. N. K. Alam, P. Roussel, M. Heyns, and J. Van Houdt, "Positive non-linear capacitance: the origin of the steep subthreshold-slope in ferroelectric FETs," Scientific Reports, vol. 9, no. 1, p. 14957, 2019/10/18 2019, doi: 10.1038/s41598-019-51237-2.
[48] E. Ko, H. Lee, Y. Goh, S. Jeon, and C. Shin, "Sub-60-mV/decade Negative Capacitance FinFET With Sub-10-nm Hafnium-Based Ferroelectric Capacitor," IEEE Journal of the Electron Devices Society, vol. 5, pp. 306-309, 2017. doi:10.1109/JEDS.2017.2731401.
[49] E. Ko, J. W. Lee, and C. Shin, "Negative Capacitance FinFET With Sub-20-mV/decade Subthreshold Slope and Minimal Hysteresis of 0.48 V," IEEE Electron Device Letters, vol. 38, pp. 418-421, 2017. doi:10.1109/LED.2017.2672967.
[50] K.-S. Li, P.-G. Chen, T.-Y. Lai, C.-H. Lin, C.-C. Cheng, C.-C. Chen, Y.-J. Wei, Y.-F. Hou, M.-H. Liao, M.-H. Lee, M.-C. Chen, J.-M. Sheih, W.-K. Yeh, F.-L. Yang, S. Salahuddin, and C. Hu, "Sub-60mV-swing negative-capacitance FinFET without hysteresis," in 2015 IEEE International Electron Devices Meeting (IEDM), 2015, pp. 22.6.1-22.6.4. doi:10.1109/IEDM.2015.7409760.
[51] M. H. Lee, S. Fan, C. Tang, P. Chen, Y. Chou, H. Chen, J. Kuo, M. Xie, S. Liu, M. Liao, C. Jong, K. Li, M. Chen, and C. W. Liu, "Physical thickness 1.x nm ferroelectric HfZrOx negative capacitance FETs," in 2016 IEEE International Electron Devices Meeting (IEDM), 2016, pp. 12.1.1-12.1.4. doi:10.1109/IEDM.2016.7838400.
[52] M. H. Lee, P.-G. Chen, S.-T. Fan, C.-Y. Kuo, H.-H. Chen, S.-S. Gu, Y.-C. Chou, C.-H. Tang, R.-C. Hong, Z.-Y. Wang, M.-H. Liao, K.-S. Li, M.-C. Chen, and C. W. Liu, "Negative capacitance FETs with steep switching by ferroelectric Hf-based oxide," in 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2017, pp. 1-2. doi:10.1109/VLSI-TSA.2017.7942466.
[53] D. Kwon, K. Chatterjee, A. J. Tan, A. K. Yadav, H. Zhou, A. B. Sachid, R. d. Reis, C. Hu, and S. Salahuddin, "Improved Subthreshold Swing and Short Channel Effect in FDSOI n-Channel Negative Capacitance Field Effect Transistors," IEEE Electron Device Letters, vol. 39, pp. 300-303, 2018. doi:10.1109/LED.2017.2787063.
[54] A. K. Yadav, K. X. Nguyen, Z. Hong, P. García-Fernández, P. Aguado-Puente, C. T. Nelson, S. Das, B. Prasad, D. Kwon, S. Cheema, A. I. Khan, C. Hu, J. Íñiguez, J. Junquera, L.-Q. Chen, D. A. Muller, R. Ramesh, and S. Salahuddin, "Spatially resolved steady-state negative capacitance," Nature, vol. 565, pp. 468-471, 2019. doi:10.1038/s41586-018-0855-y.
[55] C. H. Cheng and A. Chin, "Low-Voltage Steep Turn-On pMOSFET Using Ferroelectric High-<formula formulatype="inline"> <tex Notation="TeX">$\kappa$</tex></formula> Gate Dielectric," IEEE Electron Device Letters, vol. 35, pp. 274-276, 2014. doi:10.1109/LED.2013.2291560.
[56] R. Molaei Imen Abadi and M. Saremi, "A Resonant Tunneling Nanowire Field Effect Transistor with Physical Contractions: A Negative Differential Resistance Device for Low Power Very Large Scale Integration Applications," Journal of Electronic Materials, vol. 47, no. 2, pp. 1091-1098, 2018/02/01 2018, doi: 10.1007/s11664-017-5823-z.
[57] R. M. Imenabadi, M. Saremi, and W. G. Vandenberghe, "A Novel PNPN-Like Z-Shaped Tunnel Field- Effect Transistor With Improved Ambipolar Behavior and RF Performance," IEEE Transactions on Electron Devices, vol. 64, no. 11, pp. 4752-4758, 2017, doi: 10.1109/TED.2017.2755507.
[58] M. Saremi, A. Afzali-Kusha, and S. Mohammadi, "Ground plane fin-shaped field effect transistor (GP-FinFET): A FinFET for low leakage power circuits," Microelectronic Engineering, vol. 95, pp. 74-82, 2012/07/01/ 2012, doi: 10.1016/j.mee.2012.01.009.
[59] J.-P. Colinge et al., "Nanowire transistors without junctions," Nature Nanotechnology, vol. 5, no. 3, pp. 225-229, 2010/03/01 2010, doi: 10.1038/nnano.2010.15.
[60] C.-W. Lee et al., "Performance estimation of junctionless multigate transistors," Solid-State Electronics, vol. 54, no. 2, pp. 97-103, 2010/02/01/ 2010, doi: 10.1016/j.sse.2009.12.003.
[61] C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and J.-P. Colinge, "Junctionless multigate field-effect transistor," Applied Physics Letters, vol. 94, no. 5, p. 053511, 2009, doi: 10.1063/1.3079411.
[62] H. Lin, C. Lin, and T. Huang, "Characteristics of n-Type Junctionless Poly-Si Thin-Film Transistors With an Ultrathin Channel," IEEE Electron Device Letters, vol. 33, no. 1, pp. 53-55, 2012, doi: 10.1109/LED.2011.2171914.
[63] R. Rios et al., "Comparison of Junctionless and Conventional Trigate Transistors With $L_{g}$ Down to 26 nm," IEEE Electron Device Letters, vol. 32, no. 9, pp. 1170-1172, 2011, doi: 10.1109/LED.2011.2158978.
[64] L.-C. Chen et al., "The physical analysis on electrical junction of junctionless FET," AIP Advances, vol. 7, no. 2, p. 025301, 2017, doi: 10.1063/1.4975768.
[65] L. Chen, M. Yeh, K. Lin, M. Wu, and Y. Wu, "Junctionless Poly-Si Nanowire FET With Gated Raised S/D," IEEE Journal of the Electron Devices Society, vol. 4, no. 2, pp. 50-54, 2016, doi: 10.1109/JEDS.2016.2514478.
[66] M. Yeh, Y. Wu, M. Wu, Y. Jhan, M. Chung, and M. Hung, "High performance ultra-thin body (2.4nm) poly-Si junctionless thin film transistors with a trench structure," in 2014 IEEE International Electron Devices Meeting, 15-17 Dec. 2014 2014, pp. 26.6.1-26.6.4, doi: 10.1109/IEDM.2014.7047115.
[67] M. Yeh, Y. Wu, M. Wu, M. Chung, Y. Jhan, and M. Hung, "Characterizing the Electrical Properties of a Novel Junctionless Poly-Si Ultrathin-Body Field-Effect Transistor Using a Trench Structure," IEEE Electron Device Letters, vol. 36, no. 2, pp. 150-152, 2015, doi: 10.1109/LED.2014.2378785.
[68] V. Thirunavukkarasu et al., "Gate-all-around junctionless silicon transistors with atomically thin nanosheet channel (0.65 nm) and record sub-threshold slope (43 mV/dec)," Applied Physics Letters, vol. 110, no. 3, p. 032101, 2017, doi: 10.1063/1.4974255.
[69] Y. Lin et al., "Hybrid P-Channel/N-Substrate Poly-Si Nanosheet Junctionless Field-Effect Transistors With Trench and Gate-All-Around Structure," IEEE Transactions on Nanotechnology, vol. 17, no. 5, pp. 1014-1019, 2018, doi: 10.1109/TNANO.2018.2848283.
[70] S. Choi, J. Han, S. Kim, D. Moon, M. Jang, and Y. Choi, "A novel TFT with a laterally engineered bandgap for of 3D logic and flash memory," in 2010 Symposium on VLSI Technology, 15-17 June 2010 2010, pp. 111-112, doi: 10.1109/VLSIT.2010.5556191.
[71] H. Chen, Y. Wu, C. Chang, M. Han, N. Lu, and Y. Cheng, "Performance of GAA poly-Si nanosheet (2nm) channel of junctionless transistors with ideal subthreshold slope," in 2013 Symposium on VLSI Technology, 11-13 June 2013 2013, pp. T232-T233.
[72] P. Singh, N. Singh, J. Miao, W. Park, and D. Kwong, "Gate-All-Around Junctionless Nanowire MOSFET With Improved Low-Frequency Noise Behavior," IEEE Electron Device Letters, vol. 32, no. 12, pp. 1752-1754, 2011, doi: 10.1109/LED.2011.2169645.
[73] C. Su, T. Tsai, Y. Liou, Z. Lin, H. Lin, and T. Chao, "Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels," IEEE Electron Device Letters, vol. 32, no. 4, pp. 521-523, 2011, doi: 10.1109/LED.2011.2107498.
[74] Y. Cheng et al., "Performance enhancement of a novel P-type junctionless transistor using a hybrid poly-Si fin channel," in 2014 IEEE International Electron Devices Meeting, 15-17 Dec. 2014 2014, pp. 26.7.1-26.7.4, doi: 10.1109/IEDM.2014.7047116.
[75] Y.-C. Cheng et al., "Back-gate bias effect on nanosheet hybrid P/N channel of junctionless thin-film transistor with increased Ion versus decreased Ioff," Applied Physics Letters, vol. 107, no. 18, p. 182105, 2015, doi: 10.1063/1.4935247.
[76] Y. Cheng, H. Chen, C. Chang, C. Cheng, Y. Shih, and Y. Wu, "A highly scalable poly-Si junctionless FETs featuring a novel multi-stacking hybrid P/N layer and vertical gate with very high Ion/Ioff for 3D stacked ICs," in 2016 IEEE Symposium on VLSI Technology, 14-16 June 2016 2016, pp. 1-2, doi: 10.1109/VLSIT.2016.7573429.
[77] M. Wang, Y. Lai, S. Syu, W. Liao, W. Lan, and S. Wang, "Electrical characteristics of multi-gate P-channel FinFETs with V<inf>T</inf> implanting energies under temperature stress," in 2015 International Symposium on Next-Generation Electronics (ISNE), 2015, pp. 1-3. doi:10.1109/ISNE.2015.7131979.
[78] D. Moon, S. Choi, J. P. Duarte, and Y. Choi, "Investigation of Silicon Nanowire Gate-All-Around Junctionless Transistors Built on a Bulk Substrate," IEEE Transactions on Electron Devices, vol. 60, pp. 1355-1360, 2013. doi:10.1109/TED.2013.2247763.
[79] H. Chen, Y. Wu, C. Chang, M. Han, N. Lu, and Y. Cheng, "Performance of GAA poly-Si nanosheet (2nm) channel of junctionless transistors with ideal subthreshold slope," in 2013 Symposium on VLSI Technology, 2013, pp. T232-T233.
[80] B.-H. Lee, J. Hur, M.-H. Kang, T. Bang, D.-C. Ahn, D. Lee, K.-H. Kim, and Y.-K. Choi, "A Vertically Integrated Junctionless Nanowire Transistor," Nano Letters, vol. 16, pp. 1840-1847, 2016. doi:10.1021/acs.nanolett.5b04926.
[81] J.-P. Colinge, C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O'Neill, A. Blake, M. White, A.-M. Kelleher, B. McCarthy, and R. Murphy, "Nanowire transistors without junctions," Nature Nanotechnology, vol. 5, pp. 225, 2010. doi:10.1038/nnano.2010.15
[82] C.-W. Lee, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P. Razavi, and J.-P. Colinge, "Performance estimation of junctionless multigate transistors," Solid-State Electronics, vol. 54, pp. 97-103, 2010.
[83] R. Rios, A. Cappellani, M. Armstrong, A. Budrevich, H. Gomez, R. Pai, N. Rahhal-orabi, and K. Kuhn, " Comparison of Junctionless and Conventional Trigate Transistors With Lg Down to 26 nm," IEEE Electron Device Letters, vol. 32, pp. 1170-1172, 2011. doi:10.1109/LED.2011.2158978.
[84] L.-C. Chen, M.-S. Yeh, Y.-R. Lin, K.-W. Lin, M.-H. Wu, V. Thirunavukkarasu, and Y.-C. Wu, "The physical analysis on electrical junction of junctionless FET," AIP Advances, vol. 7, pp. 025301, 2017. doi:10.1063/1.4975768.
[85] L. Chen, M. Yeh, K. Lin, M. Wu, and Y. Wu, "Junctionless Poly-Si Nanowire FET With Gated Raised S/D," IEEE Journal of the Electron Devices Society, vol. 4, pp. 50-54, 2016. doi:10.1109/JEDS.2016.2514478.
[86] V. Thirunavukkarasu, Y.-R. Jhan, Y.-B. Liu, E. D. Kurniawan, Y. R. Lin, S.-Y. Yang, C.-H. Cheng, and Y.-C. Wu, "Gate-all-around junctionless silicon transistors with atomically thin nanosheet channel (0.65 nm) and record sub-threshold slope (43 mV/dec)," Applied Physics Letters, vol. 110, pp. 032101, 2017. doi:10.1063/1.4974255.
[87] Y. Lin, C. Cheng, Y. Jhan, E. D. Kurniawan, Y. Du, Y. Lin, and Y. Wu, "Hybrid P-Channel/N-Substrate Poly-Si Nanosheet Junctionless Field-Effect Transistors With Trench and Gate-All-Around Structure," IEEE Transactions on Nanotechnology, vol. 17, pp. 1014-1019, 2018. doi:10.1109/TNANO.2018.2848283.
[88] S. Choi, D. Moon, J. P. Duarte, S. Kim, and Y. Choi, "A novel junctionless all-around-gate SONOS device with a quantum nanowire on a bulk substrate for 3D stack NAND flash memory," in 2011 Symposium on VLSI Technology - Digest of Technical Papers, 2011, pp. 74-75.
[89] Y. S. Kim, S. Kodama, Y. Mizushima, N. Maeda, H. Kitada, K. Fujimoto, T. Nakamura, D. Suzuki, A. Kawai, K. Arai, and T. Ohba, "Ultra thinning down to 4-µm using 300-mm wafer proven by 40-nm node 2Gb DRAM for 3D multi-stack WOW applications," in 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014, pp. 1-2. doi:10.1109/VLSIT.2014.6894347.
[90] H. Lue, K. Chang, C. Chen, T. Yeh, T. Hsu, P. Du, Y. Shih, and C. Lu, "A novel bit alterable 3D NAND flash using junction-free p-channel device with band-to-band tunneling induced hot-electron programming," in 2013 Symposium on VLSI Technology, 2013, pp. T152-T153.
[91] M.-J. Tsai, Y.-Y. Chiang, Y.-R. Lin, E. Kurniawan, and Y.-C. Wu, Hybrid N-Type Poly-Si Ultra-Thin Nanowire Shell Channel with P-Substrate Structure by Electron Beam Lithography Adjustment for Junctionless Field-Effect Transistors. 2018, pp. Q201-Q205.
[92] Y. Cheng, H. Chen, C. Shao, J. Su, Y. Wu, C. Chang, and T. Chang, "Performance enhancement of a novel P-type junctionless transistor using a hybrid poly-Si fin channel," in 2014 IEEE International Electron Devices Meeting, 2014, pp. 26.7.1-26.7.4. doi:10.1109/IEDM.2014.7047116.
[93] Y.-C. Cheng, H.-B. Chen, C.-Y. Chang, Y.-K. Wu, Y.-J. Shih, C.-S. Shao, and Y.-C. Wu, "Back-gate bias effect on nanosheet hybrid P/N channel of junctionless thin-film transistor with increased Ion versus decreased Ioff," Applied Physics Letters, vol. 107, pp. 182105, 2015. doi:10.1063/1.4935247.
[94] Y. Cheng, H. Chen, C. Chang, C. Cheng, Y. Shih, and Y. Wu, "A highly scalable poly-Si junctionless FETs featuring a novel multi-stacking hybrid P/N layer and vertical gate with very high Ion/Ioff for 3D stacked ICs," in 2016 IEEE Symposium on VLSI Technology, 2016, pp. 1-2. doi:10.1109/VLSIT.2016.7573429.
[95] Interuniversity Microelectronic Centre [https://www.imec-int.com].
[96] D. Sacchetto, M. H. Ben-Jamaa, G. DeMicheli, and Y. u. Leblebici, "Fabrication and characterization of vertically stacked Gate-All-Around Si Nanowire FET arrays," in 2009 Proceedings of the European Solid State Device Research Conference, 2009, pp. 245-248. doi:10.1109/ESSDERC.2009.5331516.
[97] Y. Lu, P. Kuo, Y. Wu, Y. Chen, and T. Chao, "Novel GAA raised source / drain sub-10-nm poly-Si NW channel TFTs with self-aligned corked gate structure for 3-D IC applications," in 2011 Symposium on VLSI Technology - Digest of Technical Papers, 2011, pp. 142-143.
[98] J.-H. Lee, B.-S. Kim, S.-H. Choi, Y. Jang, S. W. Hwang, and D. Whang, "A facile route to Si nanowire gate-all-around field effect transistors with a steep subthreshold slope," Nanoscale, vol. 5, pp. 8968-8972, 2013. doi:10.1039/C3NR02552G.
[99] Sentaurus TCAD Ver. 2015, Synopsys, Mountain View, CA, USA.
[100] S. Salahuddin and S. Datta, "Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices," Nano Letters, vol. 8, pp. 405-410, 2008. doi:10.1021/nl071804g.
[101] A. I. Khan, K. Chatterjee, J. P. Duarte, Z. Lu, A. Sachid, S. Khandelwal, R. Ramesh, C. Hu, and S. Salahuddin, "Negative Capacitance in Short-Channel FinFETs Externally Connected to an Epitaxial Ferroelectric Capacitor," IEEE Electron Device Letters, vol. 37, pp. 111-114, 2016. doi:10.1109/LED.2015.2501319.
[102] A. K. Yadav, K. X. Nguyen, Z. Hong, P. García-Fernández, P. Aguado-Puente, C. T. Nelson, S. Das, B. Prasad, D. Kwon, S. Cheema, A. I. Khan, C. Hu, J. Íñiguez, J. Junquera, L.-Q. Chen, D. A. Muller, R. Ramesh, and S. Salahuddin, "Spatially resolved steady-state negative capacitance," Nature, vol. 565, pp. 468-471, 2019. doi:10.1038/s41586-018-0855-y.
[103] C. H. Cheng and A. Chin, "Low-Voltage Steep Turn-On pMOSFET Using Ferroelectric High-<formula formulatype="inline"> <tex Notation="TeX">$\kappa$</tex></formula> Gate Dielectric," IEEE Electron Device Letters, vol. 35, pp. 274-276, 2014. doi:10.1109/LED.2013.2291560.
[104] Z. Krivokapic, U. Rana, R. Galatage, A. Razavieh, A. Aziz, J. Liu, J. Shi, H. J. Kim, R. Sporer, C. Serrao, A. Busquet, P. Polakowski, J. Müller, W. Kleemeier, A. Jacob, D. Brown, A. Knorr, R. Carter, and S. Banna, "14nm Ferroelectric FinFET technology with steep subthreshold slope for ultra low power applications," in 2017 IEEE International Electron Devices Meeting (IEDM), 2017, pp. 15.1.1-15.1.4. doi:10.1109/IEDM.2017.8268393.
[105] R. Singh, K. Aditya, S. S. Parihar, Y. S. Chauhan, R. Vega, T. B. Hook, and A. Dixit, "Evaluation of 10-nm Bulk FinFET RF Performance—Conventional Versus NC-FinFET," IEEE Electron Device Letters, vol. 39, pp. 1246-1249, 2018. doi:10.1109/LED.2018.2846026.
[106] H. Zhou, D. Kwon, A. B. Sachid, Y. Liao, K. Chatterjee, A. J. Tan, A. K. Yadav, C. Hu, and S. Salahuddin, "Negative Capacitance, n-Channel, Si FinFETs: Bi-directional Sub-60 mV/dec, Negative DIBL, Negative Differential Resistance and Improved Short Channel Effect," in 2018 IEEE Symposium on VLSI Technology, 2018, pp. 53-54. doi:10.1109/VLSIT.2018.8510691.
[107] M. H. Lee, K.-T. Chen, C.-Y. Liao, S.-S. Gu, G.-Y. Siang, Y.-C. Chou, H.-Y. Chen, J. Le, R.-C. Hong, Z.-Y. Wang, S.-Y. Chen, P.-G. Chen, M. Tang, Y.-D. Lin, H.-Y. Lee, K.-S. Li, and C. W. Liu, "Extremely Steep Switch of Negative-Capacitance Nanosheet GAA-FETs and FinFETs," in 2018 IEEE International Electron Devices Meeting (IEDM), 2018, pp. 31.8.1-31.8.4.
[108] C.-J. Su, Y.-T. Tang, Y.-C. Tsou, P.-J. Sung, F.-J. Hou, C.-J. Wang, S.-T. Chung, C.-Y. Hsieh, Y.-S. Yeh, F.-K. Hsueh, K.-H. Kao, S.-S. Chuang, C.-T. Wu, T.-Y. You, Y.-L. Jian, T.-H. Chou, Y.-L. Shen, B.-Y. Chen, G.-L. Luo, T.-C. Hong, K.-P. Huang, M.-C. Chen, Y.-J. Lee, T.-S. Chao, T.-Y. Tseng, W.-F. Wu, G.-W. Huang, J.-M. Shieh, W.-K. Yeh, and Y.-H. Wang, "Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrOx on specific interfacial layers exhibiting 65% S.S. reduction and
[109] J. Wu, R. Kanyang, G. Han, J. Zhou, Y. Liu, Y. Wang, Y. Peng, J. Zhang, Q.-Q. Sun, D. W. Zhang, and Y. Hao, "Nonideality of Negative Capacitance Ge Field-Effect Transistors Without Internal Metal Gate," IEEE Electron Device Letters, vol. 39, pp. 614-617, 2018. doi:10.1109/LED.2018.2810203.
[110] E. Ko, J. W. Lee, and C. Shin, "Negative Capacitance FinFET With Sub-20-mV/decade Subthreshold Slope and Minimal Hysteresis of 0.48 V," IEEE Electron Device Letters, vol. 38, pp. 418-421, 2017. doi:10.1109/LED.2017.2672967.
[111] K.-S. Li, P.-G. Chen, T.-Y. Lai, C.-H. Lin, C.-C. Cheng, C.-C. Chen, Y.-J. Wei, Y.-F. Hou, M.-H. Liao, M.-H. Lee, M.-C. Chen, J.-M. Sheih, W.-K. Yeh, F.-L. Yang, S. Salahuddin, and C. Hu, "Sub-60mV-swing negative-capacitance FinFET without hysteresis," in 2015 IEEE International Electron Devices Meeting (IEDM), 2015, pp. 22.6.1-22.6.4. doi:10.1109/IEDM.2015.7409760.
[112] M. Si, C. Jiang, C. J. Su, Y. T. Tang, L. Yang, W. Chung, M. A. Alam, and P. D. Ye, "Sub-60 mV/dec ferroelectric HZO MoS2 negative capacitance field-effect transistor with internal metal gate: The role of parasitic capacitance," in 2017 IEEE International Electron Devices Meeting (IEDM), 2017, pp. 23.5.1-23.5.4. doi:10.1109/IEDM.2017.8268447.
[113] M. H. Lee, J. Lin, Y. Wei, C. Chen, W. Tu, H. Zhuang, and M. Tang, "Ferroelectric negative capacitance hetero-tunnel field-effect-transistors with internal voltage amplification," in 2013 IEEE International Electron Devices Meeting, 2013, pp. 4.5.1-4.5.4. doi:10.1109/IEDM.2013.6724561.
[114] J. Zhou, G. Han, N. Xu, J. Li, Y. Peng, Y. Liu, J. Zhang, Q. Sun, D. W. Zhang, and Y. Hao, "Incomplete Dipoles Flipping Produced Near Hysteresis-Free Negative Capacitance Transistors," IEEE Electron Device Letters, vol. 40, pp. 329-332, 2019. doi:10.1109/LED.2018.2886426.
[115] H. Ota, K. Fukuda, T. Ikegami, J. Hattori, H. Asai, S. Migita, and A. Toriumi, "Perspective of negative capacitance FinFETs investigated by transient TCAD simulation," in 2017 IEEE International Electron Devices Meeting (IEDM), 2017, pp. 15.2.1-15.2.4. doi:10.1109/IEDM.2017.8268394.
[116] P. J. McWhorter and P. S. Winokur, "Simple technique for separating the effects of interface traps and trapped‐oxide charge in metal‐oxide‐semiconductor transistors," Applied Physics Letters, vol. 48, pp. 133-135, 1986. doi:10.1063/1.96974.
[117] D. Kwon, K. Chatterjee, A. J. Tan, A. K. Yadav, H. Zhou, A. B. Sachid, R. d. Reis, C. Hu, and S. Salahuddin, "Improved Subthreshold Swing and Short Channel Effect in FDSOI n-Channel Negative Capacitance Field Effect Transistors," IEEE Electron Device Letters, vol. 39, pp. 300-303, 2018. doi:10.1109/LED.2017.2787063.
[118] Z. Liu, M. A. Bhuiyan, and T. P. Ma, "A Critical Examination of ‘Quasi-Static Negative Capacitance’ (QSNC) theory," in 2018 IEEE International Electron Devices Meeting (IEDM), 2018, pp. 31.2.1-31.2.4. doi:10.1109/IEDM.2018.8614614.
[119] S. Salahuddin and S. Datta, "Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices," Nano Letters, vol. 8, pp. 405-410, 2008. doi:10.1021/nl071804g.
[120] A. I. Khan, K. Chatterjee, J. P. Duarte, Z. Lu, A. Sachid, S. Khandelwal, R. Ramesh, C. Hu, and S. Salahuddin, "Negative Capacitance in Short-Channel FinFETs Externally Connected to an Epitaxial Ferroelectric Capacitor," IEEE Electron Device Letters, vol. 37, pp. 111-114, 2016. doi:10.1109/LED.2015.2501319.
[121] M. H. Lee, J. Lin, Y. Wei, C. Chen, W. Tu, H. Zhuang, and M. Tang, "Ferroelectric negative capacitance hetero-tunnel field-effect-transistors with internal voltage amplification," in 2013 IEEE International Electron Devices Meeting, 2013, pp. 4.5.1-4.5.4. doi:10.1109/IEDM.2013.6724561.
[122] T. S. Böscke, J. Müller, D. Bräuhaus, U. Schröder, and U. Böttger, "Ferroelectricity in hafnium oxide thin films," Applied Physics Letters, vol. 99, pp. 102903, 2011. doi:10.1063/1.3634052.
[123] D. Kwon, K. Chatterjee, A. J. Tan, A. K. Yadav, H. Zhou, A. B. Sachid, R. d. Reis, C. Hu, and S. Salahuddin, "Improved Subthreshold Swing and Short Channel Effect in FDSOI n-Channel Negative Capacitance Field Effect Transistors," IEEE Electron Device Letters, vol. 39, pp. 300-303, 2018. doi:10.1109/LED.2017.2787063.
[124] C.-J. Su, Y.-T. Tang, Y.-C. Tsou, P.-J. Sung, F.-J. Hou, C.-J. Wang, S.-T. Chung, C.-Y. Hsieh, Y.-S. Yeh, F.-K. Hsueh, K.-H. Kao, S.-S. Chuang, C.-T. Wu, T.-Y. You, Y.-L. Jian, T.-H. Chou, Y.-L. Shen, B.-Y. Chen, G.-L. Luo, T.-C. Hong, K.-P. Huang, M.-C. Chen, Y.-J. Lee, T.-S. Chao, T.-Y. Tseng, W.-F. Wu, G.-W. Huang, J.-M. Shieh, W.-K. Yeh, and Y.-H. Wang, "Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrOx on specific interfacial layers exhibiting 65% S.S. reduction and improved ION," in 2017 Symposium on VLSI Technology, 2017, pp. T152-T153. doi:10.23919/VLSIT.2017.7998159.
[125] J. Wu, R. Kanyang, G. Han, J. Zhou, Y. Liu, Y. Wang, Y. Peng, J. Zhang, Q.-Q. Sun, D. W. Zhang, and Y. Hao, "Nonideality of Negative Capacitance Ge Field-Effect Transistors Without Internal Metal Gate," IEEE Electron Device Letters, vol. 39, pp. 614-617, 2018. doi:10.1109/LED.2018.2810203.
[126] M. H. Park et al., "Study on the size effect in Hf0.5Zr0.5O2 films thinner than 8 nm before and after wake-up field cycling," Applied Physics Letters, vol. 107, no. 19, p. 192907, 2015. doi:10.1063/1.4935588.
[127] W. Chung, M. Si, and P. D. Ye, "Hysteresis-free negative capacitance germanium CMOS FinFETs with Bi-directional Sub-60 mV/dec," in 2017 IEEE International Electron Devices Meeting (IEDM), 2017, pp. 15.3.1-15.3.4. doi: 10.1109/IEDM.2017.8268395.
[128] J. Zhou et al., "Incomplete Dipoles Flipping Produced Near Hysteresis-Free Negative Capacitance Transistors," IEEE Electron Device Letters, vol. 40, no. 2, pp. 329-332, 2019. doi: 10.1109/LED.2018.2886426.
[129] C. H. Cheng and A. Chin, "Low-Voltage Steep Turn-On pMOSFET Using Ferroelectric High-<formula formulatype="inline"> <tex Notation="TeX">$\kappa$</tex></formula> Gate Dielectric," IEEE Electron Device Letters, vol. 35, pp. 274-276, 2014. doi:10.1109/LED.2013.2291560.
[130] E. Ko, J. W. Lee, and C. Shin, "Negative Capacitance FinFET With Sub-20-mV/decade Subthreshold Slope and Minimal Hysteresis of 0.48 V," IEEE Electron Device Letters, vol. 38, pp. 418-421, 2017. doi:10.1109/LED.2017.2672967.
[131] K.-S. Li, P.-G. Chen, T.-Y. Lai, C.-H. Lin, C.-C. Cheng, C.-C. Chen, Y.-J. Wei, Y.-F. Hou, M.-H. Liao, M.-H. Lee, M.-C. Chen, J.-M. Sheih, W.-K. Yeh, F.-L. Yang, S. Salahuddin, and C. Hu, "Sub-60mV-swing negative-capacitance FinFET without hysteresis," in 2015 IEEE International Electron Devices Meeting (IEDM), 2015, pp. 22.6.1-22.6.4. doi:10.1109/IEDM.2015.7409760.
[132] M. H. Lee, S. Fan, C. Tang, P. Chen, Y. Chou, H. Chen, J. Kuo, M. Xie, S. Liu, M. Liao, C. Jong, K. Li, M. Chen, and C. W. Liu, "Physical thickness 1.x nm ferroelectric HfZrOx negative capacitance FETs," in 2016 IEEE International Electron Devices Meeting (IEDM), 2016, pp. 12.1.1-12.1.4. doi:10.1109/IEDM.2016.7838400.
[133] C. D. Wang, C. Y. Zhu, G. Y. Zhang, J. Shen, and L. Li, "Accurate electrical characterization of forward AC behavior of real semiconductor diode: giant negative capacitance and nonlinear interfacial layer," IEEE Transactions on Electron Devices, vol. 50, pp. 1145-1148 2003. doi:10.1109/TED.2003.812480.
[134] M. Si, C. Jiang, C. J. Su, Y. T. Tang, L. Yang, W. Chung, M. A. Alam, and P. D. Ye, "Sub-60 mV/dec ferroelectric HZO MoS2 negative capacitance field-effect transistor with internal metal gate: The role of parasitic capacitance," in 2017 IEEE International Electron Devices Meeting (IEDM), 2017, pp. 23.5.1-23.5.4. doi:10.1109/IEDM.2017.8268447.
[135] Z. Krivokapic, U. Rana, R. Galatage, A. Razavieh, A. Aziz, J. Liu, J. Shi, H. J. Kim, R. Sporer, C. Serrao, A. Busquet, P. Polakowski, J. Müller, W. Kleemeier, A. Jacob, D. Brown, A. Knorr, R. Carter, and S. Banna, "14nm Ferroelectric FinFET technology with steep subthreshold slope for ultra low power applications," in 2017 IEEE International Electron Devices Meeting (IEDM), 2017, pp. 15.1.1-15.1.4. doi:10.1109/IEDM.2017.8268393.
[136] R. Singh, K. Aditya, S. S. Parihar, Y. S. Chauhan, R. Vega, T. B. Hook, and A. Dixit, "Evaluation of 10-nm Bulk FinFET RF Performance—Conventional Versus NC-FinFET," IEEE Electron Device Letters, vol. 39, pp. 1246-1249, 2018. doi:10.1109/LED.2018.2846026.
[137] H. Zhou, D. Kwon, A. B. Sachid, Y. Liao, K. Chatterjee, A. J. Tan, A. K. Yadav, C. Hu, and S. Salahuddin, "Negative Capacitance, n-Channel, Si FinFETs: Bi-directional Sub-60 mV/dec, Negative DIBL, Negative Differential Resistance and Improved Short Channel Effect," in 2018 IEEE Symposium on VLSI Technology, 2018, pp. 53-54. doi:10.1109/VLSIT.2018.8510691.
[138] M. H. Lee, K.-T. Chen, C.-Y. Liao, S.-S. Gu, G.-Y. Siang, Y.-C. Chou, H.-Y. Chen, J. Le, R.-C. Hong, Z.-Y. Wang, S.-Y. Chen, P.-G. Chen, M. Tang, Y.-D. Lin, H.-Y. Lee, K.-S. Li, and C. W. Liu, "Extremely Steep Switch of Negative-Capacitance Nanosheet GAA-FETs and FinFETs," in 2018 IEEE International Electron Devices Meeting (IEDM), 2018, pp. 31.8.1-31.8.4. doi: 10.1109/IEDM.2018.8614510.
[139] K. Xu, "Silicon MOS Optoelectronic Micro-Nano Structure Based on Reverse-Biased PN Junction," physica status solidi (a), vol. 216, p. 1800868 2019/04/01 2019. doi:10.1002/pssa.201800868.
[140] J. Müller et al., "Ferroelectricity in Simple Binary ZrO2 and HfO2," Nano Letters, vol. 12, no. 8, pp. 4318-4323, 2012/08/08 2012. doi: 10.1021/nl302049k.
[141] S. Salahuddin and S. Datta, "Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices," Nano Letters, vol. 8, pp. 405-410, 2008. doi:10.1021/nl071804g.
[142] A. I. Khan, K. Chatterjee, J. P. Duarte, Z. Lu, A. Sachid, S. Khandelwal, R. Ramesh, C. Hu, and S. Salahuddin, "Negative Capacitance in Short-Channel FinFETs Externally Connected to an Epitaxial Ferroelectric Capacitor," IEEE Electron Device Letters, vol. 37, pp. 111-114, 2016. doi:10.1109/LED.2015.2501319.
[143] D. Kwon et al., "Improved Subthreshold Swing and Short Channel Effect in FDSOI n-Channel Negative Capacitance Field Effect Transistors," IEEE Electron Device Letters, vol. 39, no. 2, pp. 300-303, 2018, doi: 10.1109/LED.2017.2787063.
[144] H. Zhou et al., "Negative Capacitance, n-Channel, Si FinFETs: Bi-directional Sub-60 mV/dec, Negative DIBL, Negative Differential Resistance and Improved Short Channel Effect," 2018 IEEE Symposium on VLSI Technology, Honolulu, HI, 2018, pp. 53-54, doi: 10.1109/VLSIT.2018.8510691.
[145] A. K. Yadav, K. X. Nguyen, Z. Hong, P. García-Fernández, P. Aguado-Puente, C. T. Nelson, S. Das, B. Prasad, D. Kwon, S. Cheema, A. I. Khan, C. Hu, J. Íñiguez, J. Junquera, L.-Q. Chen, D. A. Muller, R. Ramesh, and S. Salahuddin, "Spatially resolved steady-state negative capacitance," Nature, vol. 565, pp. 468-471, 2019. doi:10.1038/s41586-018-0855-y.
[146] J. Xu, S.-Y. Jiang, M. Zhang, H. Zhu, L. Chen, Q.-Q. Sun, and D. W. Zhang, "Ferroelectric HfZrOx-based MoS2 negative capacitance transistor with ITO capping layers for steep-slope device application," Appl. Phys. Lett., vol. 112, no. 10, Mar. 2018, Art. no. 103104, doi: 10.1063/1.5019418.
[147] M. Hoffmann, A. I. Khan, C. Serrao, Z. Lu, S. Salahuddin, M. Pešić, S. Slesazeck, U. Schroeder, and T. Mikolajick, "Ferroelectric negative capacitance domain dynamics," J. Appl. Phys., vol. 123, no. 18, May. 2018, Art. no. 184101, doi: 10.1063/1.5030072.
[148] M. J. Tsai, P. J. Chen, C. C. Hsu, D. B. Ruan, F. J. Hou, P. Y. Peng, and Y. C. Wu, "Atomic-Level Analysis of Sub-5-nm-Thick Hf0.5Zr0.5O2 and Characterization of Nearly Hysteresis-Free Ferroelectric FinFET," IEEE Electron Device Lett., vol. 40, no. 8, pp. 1233-1236, 2019, doi: 10.1109/LED.2019.2922239.
[149] R. K. Jana, "A Non-Hysteretic Sub-60-mV/decade Subthreshold Slope and ON-Current Boosts in Electrostrictive-Piezoelectric Transistors," IEEE Electron Device Letters, vol. 38, pp. 1759-1762, 2017. doi:10.1109/LED.2017.2766601.
[150] J. Íñiguez, P. Zubko, I. Luk’yanchuk, and A. Cano, "Ferroelectric negative capacitance," Nat. Rev. Mater., vol. 4, no. 4, pp. 243-256, Apr, 2019, doi: 10.1038/s41578-019-0089-0.
[151] G. A. Salvatore, A. Rusu, and A. M. Ionescu, "Experimental confirmation of temperature dependent negative capacitance in ferroelectric field effect transistor," Appl. Phys. Lett., vol. 100, no. 16, Apr. 2012, Art. no. 163504, doi: 10.1063/1.4704179.
[152] A. I. Khan, K. Chatterjee, B. Wang, S. Drapcho, L. You, C. Serrao, S. R. Bakaul, R. Ramesh, and S. Salahuddin, "Negative capacitance in a ferroelectric capacitor," Nat. Mater., vol. 14, no. 2, pp. 182-186, Feb. 2015, doi: 10.1038/NMAT4148.
[153] D. Moon, S. Choi, J. P. Duarte, and Y. Choi, "Investigation of Silicon Nanowire Gate-All-Around Junctionless Transistors Built on a Bulk Substrate," IEEE Transactions on Electron Devices, vol. 60, no. 4, pp. 1355-1360, 2013, doi: 10.1109/ted.2013.2247763.
[154] Y.-M. Niquet, H. Mera, and C. Delerue, "Impurity-limited mobility and variability in gate-all-around silicon nanowires," Appl. Phys. Lett., vol. 100, no. 15, Apr. 2012, Art. no. 153119, doi: 10.1063/1.4704174.
[155] M.-F. Hung, Y.-C. Wu, and Z.-Y. Tang, "High-performance gate-all-around polycrystalline silicon nanowire with silicon nanocrystals nonvolatile memory," Appl. Phys. Lett., vol. 98, no. 16, Apr. 2011, Art. no. 162108, doi: 10.1063/1.3582925.
[156] J.-P. Colinge, C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O'Neill, A. Blake, M. White, A.-M. Kelleher, B. McCarthy, and R. Murphy, "Nanowire transistors without junctions," Nat. Nanotechnol., vol. 5, no. 3, pp. 225-229, Mar. 2010, doi: 10.1038/nnano.2010.15.
[157] L.-C. Chen, M.-S. Yeh, Y.-R. Lin, K.-W. Lin, M.-H. Wu, V. Thirunavukkarasu, and Y.-C. Wu, "The physical analysis on electrical junction of junctionless FET," AIP Adv., vol. 7, no. 2, p. 025301, Feb. 2017, doi: 10.1063/1.4975768.
[158] V. Thirunavukkarasu, Y.-R. Jhan, Y.-B. Liu, E. D. Kurniawan, Y. R. Lin, S.-Y. Yang, C.-H. Cheng, and Y.-C. Wu, "Gate-all-around junctionless silicon transistors with atomically thin nanosheet channel (0.65 nm) and record sub-threshold slope (43 mV/dec)," Appl. Phys. Lett., vol. 110, no. 3, Jan. 2017, Art. no. 032101, doi: 10.1063/1.4974255.
[159] M. J. Tsai, Y. Y. Chiang, Y. R. Lin, E. D. Kurniawan, and Y. C. Wu, “Hybrid N-Type Poly-Si Ultra-Thin Nanowire Shell Channel with P-Substrate Structure by Electron Beam Lithography Adjustment for Junctionless Field-Effect Transistors,” ECS J. Solid State Sci. Technol., 7, pp. 201-205, 2018, doi: 10.1149/2.0111811jss.
[160] Y. Cheng, H. Chen, C. Shao, J. Su, Y. Wu, C. Chang, and T. Chang, "Performance enhancement of a novel P-type junctionless transistor using a hybrid poly-Si fin channel," IEEE Int. Electron Devices Meet., 2014, pp. 26.7.1-26.7.4., doi: 10.1109/iedm.2014.7047116.
[161] B. Obradovic, T. Rakshit, R. Hatcher, J. A. Kittl and M. S. Rodder, "Modeling Transient Negative Capacitance in Steep-Slope FeFETs," in IEEE Transactions on Electron Devices, vol. 65, no. 11, pp. 5157-5164, Nov. 2018, doi: 10.1109/TED.2018.2868479.
[162] J. A. Kittl, B. Obradovic, D. Reddy, T. Rakshit, R. M. Hatcher, and M. S. Rodder, "On the validity and applicability of models of negative capacitance and implications for MOS applications," Applied Physics Letters, vol. 113, no. 4, p. 042904, 2018, doi: 10.1063/1.5036984.
[163] F. Hou, P. Sung, F. Hsueh, C. Wu, Y. Lee, Y. Li, S. Samukawa, and T. Hou, "Suspended Diamond-Shaped Nanowire With Four {111} Facets for High-Performance Ge Gate-All-Around FETs," IEEE Transactions on Electron Devices, vol. 63, pp. 3837-3843, 2016. doi:10.1109/TED.2016.2597317.
[164] Y. Lee, F. Hou, S. Chuang, F. Hsueh, K. Kao, P. Sung, W. Yuan, J. Yao, Y. Lu, K. Lin, C. Wu, H. Chen, B. Chen, G. Huang, H. J. H. Chen, J. Li, Y. Li, S. Samukawa, T. Chao, T. Tseng, W. Wu, T. Hou, and W. Yeh, "Diamond-shaped Ge and Ge0.9Si0.1 gate-all-around nanowire FETs with four {111} facets by dry etch technology," in 2015 IEEE International Electron Devices Meeting (IEDM), 2015, pp. 15.1.1-15.1.4. doi:10.1109/IEDM.2015.7409701.
[165] C. Su, Y. Tang, Y. Tsou, P. Sung, F. Hou, C. Wang, S. Chung, C. Hsieh, Y. Yeh, F. Hsueh, K. Kao, S. Chuang, C. Wu, T. You, Y. Jian, T. Chou, Y. Shen, B. Chen, G. Luo, T. Hong, K. Huang, M. Chen, Y. Lee, T. Chao, T. Tseng, W. Wu, G. Huang, J. Shieh, W. Yeh, and Y. Wang, "Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrOx on specific interfacial layers exhibiting 65% S.S. reduction and improved ION," in 2017 Symposium on VLSI Technology, 2017, pp. T152-T153. doi:10.23919/VLSIT.2017.7998159.
[166] J. Müller, T. S. Böscke, U. Schröder, S. Mueller, D. Bräuhaus, U. Böttger, L. Frey, and T. Mikolajick, "Ferroelectricity in Simple Binary ZrO2 and HfO2," Nano Letters, vol. 12, pp. 4318-4323, 2012. doi:10.1021/nl302049k.

簡易檢索 / 詳目顯示

相關論文