我們在這篇論文中提出一個針對先進影像壓縮技術(H.264 Advance Video Coding)的移動補償硬體加速器。我們的設計包含所有先進技術的特性：在動態估計可以使用不同的區塊大小(variable block size)、支援多個參考畫面(multiple reference frame)、支援單一方向的畫面預測(P slice)和兩個方向的畫面預測(B slice)、1/4畫素精確度、不同比重的畫面預估(weight prediction)。為了減少記憶體頻寬(memory bandwidth)和有效的記憶體使用方法(memory usage)，我們花了很多時間設計一個新的記憶體儲存架構。我們將此一硬體加速器整合到先進影像壓縮技術的解壓縮器(H.264 decoder)中並做了可程式畫邏輯元件(FPGA)的原型(prototype)。跟先前的設計比較起來，我們的加速器比較小而且較快。

We propose a hardware accelerator for H.264/AVC motion compensation. Our design supports advanced features including variable-block-size motion estimation from multiple reference frames for both P and B slices, quarter-pixel accuracy, and weighted bi-directional prediction. We pay special attention to memory subsystem design for optimizing both memory usage and memory bandwidth. We have integrated the accelerator into an H.264/AVC main profile decoder in FPGA prototype. Compared with previous work, our accelerator is smaller and faster.

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