更好的效能，一直是積體電路設計的目標之一。由於設計工具的可用性和簡化設計方法，同步電路設計已經為今天的積體電路設計的主要設計方法。同步電路需要一個全域時脈信號，這個時脈樹已被證明消耗總功率很大一部分。
此外，由於時脈頻率被提升到數十倍千兆赫茲範圍內，時脈抖動和傾斜便扮演了更重要的角色。非同步設計方法不需全域時脈，因此可以提高的效能。為了真正得到非同步設計的優點，完成檢測信號必需被產生，以表示完成當前任務，並開始下一個任務。
一個很好的完成檢測電路應該是能夠產生完成訊號並僅使用非常小的花費在面積，功耗和延遲時間。在這篇論文中提出一個基於輸入模式檢測完成方法。大的電路塊被分成更小的電路塊;如此對於一個單獨的電路塊僅需要小面積;權衡被檢測輸入樣式的個數和電路複雜度可以被利用，內部完成信號在各電路塊之間，可進一步減少完成電路的複雜性;合併電路，結合各自完成信號，以形成整體的完成信號也進行了研究。結合所有技術，展示5位元RCA的完成信號，可在平均延遲時間快17％的速度比最壞的情況下的延遲，並與綁定數據的方法相比，用小3.5倍的面積。

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