可靠度是設計積體電路時的一個重要議題，許多可靠度的問題都和邏輯閘的開關行為(switching activity)有關。例如，若邏輯閘出現頻繁的開關動作，會造成嚴重的噪訊及耗電；又若電路的輸出上發生太晚出現的開關動作，則會違反電路的時序要求，甚至造成運算結果錯誤。在本論文中，我們提出幾個理論和邏輯閘的開關行為有關，並根據這些理論發展演算法，來解決幾個可靠度的問題。這些問題描述如下。
首先，我們解決最大瞬間電流的分析問題。我們提出兩種方法, 一種是去找出能造成最大電流的緊下限值的輸入值向量(input vector)。另一種則不找輸入值向量，而是靜態地估算出緊上限值。通常靜態方法是去找出一組邏輯閘能同時開關產生最大電流。已知訊號間交互作用(signal correlation)會限制邏輯閘間同時開關的發生，在本論文中，我們深入地研究訊號間的交互作用。值得一提的是，我們應該是第一個研究循序元件造成的訊號間交互作用。因此，我們能比過去的方法算出更準確的最大瞬間電流值。
接著，關於找出輸入值向量，這個問題可轉成「考慮時序的自動測試向量產生」(timed ATPG)的問題。不像傳統的作法直接去發展複雜的「考慮時序的自動測試向量產生」的解法，我們提出一個方法能有效率地建出時序特徵函式(timed characteristic function)。據此，「考慮時序的自動測試向量產生」問題能轉成傳統的「自動測試向量產生」（ATPG）問題, 然後我們就能應用已發展的很好的傳統的「自動測試向量產生」解法來找出輸入值向量。
最後，我們提出一個新的重新合成的方法能使得一個電路變得容忍時序變動(delay variation)，進而提高電路的時序良率(timing yield)。不像傳統的方法去犧牲時序，我們的方法加入一些額外邏輯閘來達到要求的時序變動容忍度。事實上，實驗結果顯示平均上，我們的方法花費17%的額外電路面積，將時序良率從77%提高到88%。

Reliability is an important issue of designing VLSI chips. Many reliability problems are related to switching activity in a circuit. For example, frequent switching of gates can cause severe noise and power, and late switching at primary outputs can induce timing violation and even malfunction. In this thesis we propose theorems related to switching of gates, and based on those theorems, we develop algorithms to solve problems about VLSI reliability. The problems are described as follows.
We first focus on the problem of analyzing the maximum instantaneous current (MIC) of a circuit. We propose two different ways to solve this problem. One is to find the worst-case input vectors that activate a tight lower bound of the MIC; one is to estimate a tight upper bound of the MIC in a static way without vectors. Usually static analysis aims at finding a large set of gates switching simultaneously to contribute the MIC. It is well known that signal correlation restricts the simultaneous switching of gates. In this thesis we well study signal correlation and specially, we should be the first to study the signal correlation due to sequential elements. With this knowledge we can derive a tighter upper bound of the MIC than previous methods.
Next, about finding the worst-case vectors, the problem can be modeled as the timed ATPG problem. Unlike traditional approaches to developing complex timed ATPG solvers, we propose a method to efficiently construct transition-mode timed characteristic function (TCF), with which the timed ATPG can be reduced to the (conventional) ATPG problem. Then we adopt well-developed (conventional) ATPG or SAT solvers to generate the worst-case vectors.
Finally, we propose a novel re-synthesis method for making a circuit become tolerate delay variation, thus improving the timing yield of the circuit. Unlike traditional methods of sacrificing circuit timing, our method adds a small amount of redundant gates to achieve a given degree of delay tolerance. In fact, the experimental results show that on average, our method costs 17% area overhead to improve the timing yield from 77% to 88%.

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