在這篇論文中，我們建議了兩種對於系統封裝(System-In-Package)
分割的方法，首先，我們建議了整數線性規畫(Integer Linear
Programming)的方法來解決此系統封裝分割的問題.接下來，我們也
建議了模擬退火(Simulated Annealing)的方法來解決系統封裝分割
的問題.我們的系統封裝分割的目標是最小化，不同層的總線長長度
(total length of inter-layer connections)，消耗總墊子數(I/O
Pads)，溫度(temperature)，與平面的連線總長度(on-chip
wire-length).實驗結果顯示，我們模擬退火方法改進，不同層的總
線長長度0.31%~7.72%，消耗總墊子數0.34%~3.31%，溫度
0.83%~11.74%與平面的連線總長度0.05%~2.8%在與hmetis 比較的結
果之下.

In this thesis, we have presented two partitioning approaches for a die-stacking SiP design.
First, we use Integer Linear Programming (ILP) based method to solve this problem.
Second, we use Simulated Annealing (SA) based method to solve this problem. Our SiP
partitioning goal is to minimize total length of inter-layer connections, total I/O pads, onchip
wire-length and temperature in order to get better performance. The experimental
results on the Gigascale Systems Research Center (GSRC) benchmarks show that our SA
based method improves the total length of inter-layer connections by 0.31%-7.72%, total
I/O pads by 0.34% - 3.13%, temperature by 0.83% - 11.74% and on-chip wire-length by
0.05% - 2.8% compared with hmetis [10].

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[10] http://glaros.dtc.umn.edu/gkhome/
[11] http://www.necel.com
[12] http://en.wikipedia.org/wiki/