簡易檢索 / 詳目顯示

研究生: 賴琇瑜
Lai, Hsiu-Yu
論文名稱: 具列結構標準元件三重圖案微影技術合法化方法
A TPL-Friendly Legalizer for Cell-Based Row-Structure Layout
指導教授: 王廷基
Wang, Ting-Chi
口試委員: 李毅郎
Li, Yih-Lang
陳宏明
Chen, Hung-Ming
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年: 2013
畢業學年度: 101
語文別: 英文
論文頁數: 25
中文關鍵詞: 三重圖案微影技術合法化方法
外文關鍵詞: TPL, Legalizer
相關次數: 點閱:1下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 隨著feature size 的縮小以及下世代光罩發展的延遲,
    DPL(Double Patterning Lithography)已不足以用在14/10 奈米的技
    術之上。TPL(Triple Patterning Lithography)是 DPL 的延伸,它
    不僅能將pitch 增為三倍也能減少stitch 的使用以及存在於DPL 的
    Native Conflict。雖然TPL 比起DPL 要來的更加複雜與困難,但TPL
    可以實行在14/10 奈米的技術之上。在本論文中,我們將TPL 的考慮
    放在legalization 的階段裡去產生一個更有利於分解的結果。我們
    將利用重新排列cell 順序以及安插White space 來減少TPL conflict
    的產生。在這個實驗結果裡,我們的legalizer 比起目前現有的
    legalizer 可以減少更多的TPL conflict 及stitch。


    As the shrinking of the feature size and the delay of the next generation lithography, double patterning lithography (DPL) is no longer enough for 14/10nm technology. Triple patterning lithography (TPL) is a nature extension from DPL, and it can not only triple the pitch but also reduce stitches and native conflicts. Although TPL is more difficult and complicated than DPL, TPL is inevasible for 14/10nm technology. In this thesis, we consider TPL during the standard cell legalization stage in order to let the resultant placement be more friendly to TPL decomposition. We provide a novel idea of reducing TPL conflicts through cell reordering and white space insertion. The experimental results show that as compared to a conventional legalizer, our legalizer is able to effectively reduce the number of conflicts and the number of stitches.

    1 Introduction 1 2 Problem Formulation 6 3 Our Legalizer 8 3.1 Initial Legal Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 Cell Reordering and White Space Insertion . . . . . . . . . . . . . . . . . . 9 3.2.1 Cell Reordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2.1.1 Cell Reordering by Grouping . . . . . . . . . . . . . . . . 11 3.2.1.2 Refinement . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.2 White Space Insertion . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 Experimental Results 17 4.1 Experiments on 2008 MOE IC/CAD Contest Benchmarks . . . . . . . . . 18 4.2 Experiments on Random Benchmarks . . . . . . . . . . . . . . . . . . . . 18 5 Conclusions 23

    [1] D. Hill. Method and system for high speed detailed placement of cells within inte-grated circuit design. U.S. Patent, 6370673, 2002.
    [2] A. van Oosten, P. Nikolsky, J. Huckabay, R. Goossens, and R. Naber. Pattern split rules!a feasibility study of rule based pitch decomposition for doublepatterning. SPIE
    Photomask Technology, 6730:67301L, 2007.
    [3] D. Z. Pan, J. Yang, K. Yuan, M. Cho, and Y. Ban. Layout optimizations for double patterning lithography. ASIC, pages 726 - 729, 2009.
    [4] A. B. Kahng, C.-H. Park, X. Xu, and H. Yao. Layout decomposition approaches for double patterning lithography. IEEE Transactions on CAD, 29(6):939-952, 2010.
    [5] S.-Y. Chen and Y.-W. Chang. Native-conflict-aware wire perturbation for double patterning technology. ICCAD, pages 556-561, 2010.
    [6] K. Yuan, J. Yang, and D. Z. Pan. Double patterning layout decomposition for simultaneous conflict and stitch minimization. IEEE Transactions on CAD, 29(2):185-196, 2010.
    [7] B. Yu, K. Yuan, B. Zhang, D. Ding, and D. Z. Pan. Layout decomposition for triple patterning lithography. ICCAD, pages 1-8, 2011.
    [8] Q. Ma, H. Zhang, and M. D. F. Wong. Triple patterning aware routing and its comparison with double patterning aware routing in 14nm technology. DAC, pages 591-596, 2012.
    [9] H. Tian, H. Zhang, Q. Ma, Z. Xiao, and M. D. F. Wong. A polynomial time triple patterning algorithm for cell based row-structure layout. ICCAD, pages 57 - 64, 2011.
    [10] S.-Y. Fang, Y.-W. Chang, and W.-Y. Chen. A novel layout decomposition algorithm for triple patterning lithography. DAC, pages 1181-1186, 2012.
    [11] P. Spindler, U. Schlichtmann, and F.M. Johannes. Abacus: Fast legalization of standard cell circuits with minimal movement. ISPD, pages 47-53, 2008.
    [12] N. Viswanathan, M. Pan, and C. Chu. Fastplace 3.0: a fast multilevel quadratic placement algorithm with placement congestion control. ASP-DAC, pages 135-140, 2007.
    [13] K. Doll, F. M. Johannes, and K.J. Antreich. Iterative placement improvement by network ow methods. IEEE Transactions on CAD, 13(10):1189-1200, 1994.
    [14] M. Cho, H. Ren, H. Xiang, and R. Puri. History-based vlsi legalization using network flow. DAC, pages 286-291, 2010.
    [15] LEDA package. URL http://www.algorithmic-olutions.com/.
    [16] A. B. Kahng, P. Tucker, and A. Zelikovsky. Optimization of linear placements for wirelength minimization with free sites. ASP-DAC, pages 241-244, 1999.
    [17] 2008 MOE IC/CAD Contest. URL http://cad_contest.cs.nctu.edu.tw/cad11/.
    [18] Open Cell Library. URL https://www.si2.org/.

    無法下載圖示 全文公開日期 本全文未授權公開 (校內網路)
    全文公開日期 本全文未授權公開 (校外網路)

    QR CODE