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研究生: 陳育廷
Chen, Yu-Ting
論文名稱: 先進金氧半場效電晶體之低頻雜訊特性研究
Low-Frequency Noise Characterization of Advanced Metal-Oxide-Semiconductor Field-Effect-Transistors
指導教授: 葉鳳生
口試委員: 葉鳳生
張廖貴術
葉文冠
陳坤明
黃國威
學位類別: 博士
Doctor
系所名稱: 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年: 2011
畢業學年度: 99
語文別: 英文
論文頁數: 105
中文關鍵詞: 低頻雜訊
外文關鍵詞: Low frequency noise, Flicker noise, SiGe, high-k, FinFET
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  • In order to achieve the faster operation speed, lower power consumption, and higher packing density, the advanced complementary metal-oxide-semiconductor field-effect-transistors (CMOSFETs) has become the prevailing device for silicon very-large-scale-integrated (VLSI) circuits. However, complex manufacturing technologies, new materials, and new device architectures will strongly influence on low-frequency noise (flicker noise, 1/f noise) characterization and device reliability.
    The main topic of this thesis is the flicker noise characterization in advanced MOSFETs, including strained SiGe-channel with highly compressive stressing layer devices, high-κ/metal-gate with gadolinium (Gd) cap layer devices, and symmetric double-gate (DG) SOI-FinFETs. We demonstrated that the SiGe-channel device with a highly compressive contact-etching stop-layer (CESL) interlayer-dielectric-SiNx stressing layer have higher drain current, effective mobility and lower flicker noise than conventional SiGe-channel and bulk-Si devices. However, the device reliability is degraded while integrating with the CESL stressing layer. It may be due to more Si-H bonds exist in gate-oxide and at the oxide/Si interface when a highly compressive CESL stressing layer is deposited. For the high-κ/metal-gate NMOSFET with Gd cap layer, we demonstrated that incorporated nitrogen could suppress Gd diffusion in a high-κ gate-dielectric and thus reduce the interfacial- and bulk-trap densities. The device performance, hot-carrier instability (HCI) and flicker noise characterization can be improved apparently. The flicker noise characterization of symmetric DG p-channel SOI-FinFETs with varied aspect ratio of Si-fin (the fin height/the fin width) from weak- to strong-inversion is also investigated in this thesis. We demonstrated that the device performance of thinner Si-fin width (Wfin) devices might be degraded due to the parasitic source/drain (S/D) series resistance effect. Moreover, in high current region, the parasitic S/D series resistance also strongly influences the flicker noise characterization, especially in higher Si-fin height (Hfin) devices.


    Abstract………………………………...……………………………………………i 摘要……………………………………………………………...…………………..iii Acknowledgment.....................................................................................................v Contents.....................................................................................................................vi Figure Captions……………………………………....................………………...ix Table Captions………………………………......................……………....……..xv Chapter I Introduction………………………………………………..….……...1 1.1 Advanced CMOS Devices……………………………………………………..…..2 1.2 Flicker Noise Measurement in Advanced CMOS Devices….…........................….6 1.3 Thesis Organization………………………………………………………..…...….6 Chapter II Flicker Noise Model and Measurement…….………………...8 2.1 Correlated Carrier-Number-Mobility Fluctuation Model……………………..…..9 2.2 Hooge’s Bulk-Mobility Fluctuation Model……………………………………....12 2.3 Flicker Noise Measurement Setup…………………………….....…………...….14 Chapter III Impact of High-Compressive SiNx Stressing Layer on Flicker Noise and Reliability in SiGe-Channel PMOSFETs…………………………………………..……….…16 3.1 Introduction………………………………………………………………….…...17 3.2 Experiment Procedures……………………………………………………….…..18 3.3 Devices Performance……………………………………………………………..20 3.4 Charge-Pumping and Flicker Noise Results………………..……………………24 3.5 Hot-Carrier Stress Effect on Flicker Noise…………………….………………...37 3.6 Summary...………………………………………………………………………..41 Chapter IV Effect of NH3 Plasma Nitridation on Flicker Noise and Reliability in Gd-Doped High-κ Gate-Dielectric NMOSFETs…….……………………………………...……...…42 4.1 Introduction………………………………………………………………...…….43 4.2 Experiment Procedures…………………………………………………….…......45 4.3 Devices Performance and Reliability…………………….…..………….…..…...46 4.4 Charge-Pumping and Flicker Noise Results……………………..………..…..…52 4.5 Hot-Carrier Stress Effect on Flicker Noise……………………..…………......…59 4.6 Summary…………………...…………………………………...…………….….63 Chapter V Investigation of Flicker Noise in Symmetric Double-Gate P-Channel SOI-FinFETs from Weak- to Strong-Inversion…………………………………………………64 5.1 Introduction……………………………………………………………............... 65 5.2 Experiment Procedures………………………………………………......….…... 66 5.3 Devices Performance……………………………………………………………..68 5.4 Flicker Noise Results……………………...……...………………...…..……......71 5.5 Summary..…………………………….…......................................................…....80 Chapter VI Conclusions and Future Work...…………………..……..…..81 6.1 Conclusions………………………………………………………………………81 6.2 Future Work………………………………………………………………………83 Reference………………………………………………………….……………….84 Vita……………………………………………………………………..………......103 Publication List………………………………………………….………….......104

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