近年來積體電路的快速發展，帶動整個消費性電子的產品日新月異，能夠降低成本的系統單晶片越來越多，其中擔任介面的類比數位轉換器或數位類比轉換器也越顯的重要。許多可攜式的產品譬如手機、無線耳機等等，使用一般乾電池或充電電池當作電源供應，因此功率的消耗被要求在一定的範圍。而以無線通訊系統來說，高資料傳輸速率也要求更快的類比數位轉換器，因此高速低功率的類比數位轉換器成為現代設計的趨勢了。本文將傳統的三種架構：雙取樣保持電路、單級1.5位元的脈管式類比數位轉換器、時間交錯式(平行式)類比數位轉換器，透過運算放大器、比較器的共用來結合，加上每級電容最佳化，達到高轉換速度低功率消耗的目的。在光罩的成本做考量下，我們採用TSMC 0.35um 1p4m Technology的製程進行HSPICE的全部模擬，並且為了減少功率消耗而將比較器與數位電路部分供應電壓降為2.5V，經模擬證實是可行的。我們完成一個8位元100MS/s的類比數位轉換器，並且再輸入訊號頻率約20MHz時仍有7位元以上的有效位元數，並且為83mW的功率消耗。

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