現今的晶片由多個不同的電路方塊所組成，而傳統上每個電路方塊是由同個標準元件庫所構成，標準元件庫通常會被設計成多種不同元件高度供選擇(例如在28奈米製程中有9軌和12軌高度的標準元件庫)，每個標準元件庫皆由相同高度的元件所組成，高度較高的標準元件相較於高度較低的標準元件提供較好的效能但相對地會有較大的面積和功耗，因此一個聰明的設計策略乃是混合使用不同高度的標準元件庫來達到更好的設計品質。根據參考文獻中的[1]，我們提出了一個改良型的混合高度標準元件擺放流程，我們在初始擺放階段與初始區域決定階段使用相同流程但不同的群聚方法去改良[1]，同時在區域限制擺放階段開發了新的方法。前景看好的實驗結果展示了我們的流程相較於[1]更加優越。

There are various digital circuit blocks in a modern IC, and each block is typically made of standard cells all from a single standard cell library. Standard cell libraries are usually designed with different cell-heights (e.g., 9-track and 12-track cell libraries in a 28nm node) while each library contains standard cells of the same height. A standard cell of larger height provides better performance but inversely has larger area and consumes more power than one with smaller height. As a result, a smart strategy for designing a digital circuit block should try to mix the usage of cells with different heights for achieving better design quality. Based on a previous work [1] in this thesis, we present an improved mixed-height standard cell placement flow for digital circuit blocks. We enhance the placement flow of [1] by using the same flow but different clustering method in initial placement stage and initial region determination stage, and developing a different method to generate a mixed-height standard cell placement in region-constrained placement stage. Promising experimental results are reported to demonstrate the superiority of our placement flow over [1].

[1] Y.-C. Zhao, A Mixed-HeightStandardCellPlacementFlowandItsImplementation. Master
Thesis, NationalTsingHuaUniversity,2018.
[2] I. Markov,J.Hu,andM.-C.Kim,“Progressandchallengesinvlsiplacementresearch,”in
Proc.ICCAD, pp.275–282,2012.
[3] M. Wang,X.Yang,andM.Sarrafzadeh,“Dragon2000:standard-cellplacementtoolforlarge
industry circuits,”in Proc.ICCAD, pp.260–263,2000.
[4] C. SechenandA.Sangiovanni-Vincenttelli,“Thetimberwolfplacementandroutingpackage,”
in IEEE JounralofSolid-StateCircuits, vol.SC-20,pp.510–522,1985.
[5] A. E.Caldwell,A.B.Kahng,andI.L.Markov,“Optimalpartitionersandend-caseplacers
for standard-celllayout,”in IEEE Trans.Computer-AidedDesign, vol.19,pp.1304–1313,
2000.
[6] M. C.YildizandP.H.Madden,“Improvedcutsequencesforpartitioningbasedplacement,”
in Proc.DAC, pp.776–779,2001.
[7] P.SpindlerandF.M.Johannes,“Fastandrobustquadraticplacementcombinedwithan
exact linearnetmodel,”in Proc.ICCAD, pp.179–186,2006.
[8] P.Gupta,A.B.Kahng,S.Nakagawa,S.Shah,andP.Sharma,“Mixedcell-heightimple-
mentationforimproveddesignqualityinadvancednodes,”in Proc.ICCAD, pp.854–860,
2015.
[9] S. v.Dongen, GraphClusteringbyFlowSimulation. PhDthesis,UniversityofUtrecht,2000.
[10] R. A.JarvisandE.A.Patrick,“Clusteringusingasimilaritymeasurebasedonsharednear
neighbors,”in Proc.IEEETrans.Comput., vol.C-22,pp.1025–1034,1973.
[11] Synopsys DesignCompiler. http://www.synopsys.com.
[12] OpenCoresDesign. http://opencores.org/.
[13] CadenceInnovus. http://www.cadence.com.