摘要
縮小元件的尺寸藉以提昇電路及整個系統的效能已經成為主要努力的目
標。然而縮小元件尺寸雖然帶來不少利益，卻也會造成積體電路之間的傳輸效應
某種程度的損耗。其間如寄生的電阻、電容和電感效應將會開始影響電路的效
能，此效應在深次微米ULSI 技術尤其顯著。在第二章中，將討論各種CMOS
積體電路間傳輸線的結構，以更了解各種結構間的損耗及延遲。
隨著操做頻率不斷提高，微波積體電路結構將迫切需要高品質因數的被動元
件，例如些高效能、高穩定度的濾波器以及低相位雜訊的振盪器。此外，將微波
積體電路和CMOS 製程結合以降低成本已經是現在積體電路設計者的主要目
標。在第三章中，以CMOS 製程設計一高品質因數的多重耦合共振腔濾波器。
其量測出之loaded 及unloaded Q 分別為38 及83。
在第四章中，利用CMOS 製程設計一具有相當高效能的平衡式放大器。3dB
藍基耦合器也藉由多層金屬的CMOS 製程設計出。此平衡式放大器的操作頻寬
為7.5 GHz，而其增益為18-21 dB。

ABSTRACT
To enhance the circuit and system performance, the major effort has been
focused on improving the device speed through scaling of device dimensions. The
decrease in minimum feature size of devices has led to a property decrease in
interconnect cross-sectional area and pitch. The parasitic resistance, capacitance, and
inductance associated with interconnects are beginning to influence the circuit
performance and the evolution of deep sub-micron ULSI technology. Therefore, in
chapter 2, variable structures of Si-based IC interconnects are discussed, and a deeper
understanding of the loss and delay characteristics is obtained. The trade-offs of
different designs are also addressed.
As operation frequency keep increasing, microwave IC structures have suffered
from a lack of high Q miniature passive elements, which have applications such as
high-performance filters and low-phase noise oscillators. Furthermore, that millimeter
microwave integrated-circuit combine with CMOS technology to decrease cost is the
current trend for MMIC design. In chapter 3, a high Q, multiple-ring resonant filter is
designed in a standard 0.18 µm CMOS process. The measurement results show a
loaded and unloaded Q of 38 and 83, respectively.
In chapter 4, a high-performance Ka-band balanced amplifier is designed in a
standard 0.18 µm. A 3-dB Lange coupler is designed using the multiple-interconnect
process of CMOS. A bandwidth of 7.5 GHz and a maximan gain of 21 dB are
obtained.

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