隨著半導體製程技術的不斷演進，金氧互補式半導體(CMOS)的尺寸縮小至百奈米以下，同時數位電路之核心供給電壓也下降到一伏特甚至以下。然而對於一般的數位電路設計者而言，要將數千萬或上億顆的邏輯閘進行人工的設計是不可行的，因此標準元件設計流程(Cell-based design flow)便取代傳統流程成為市面上主流的數位電路設計標準流程。

本論文為數位電路設計者提供了一具有功率意識且可執行雙重電壓配給技術之標準元件庫以及流程設計。標準元件庫的設計除了需要耗費龐大的人力與時間之外，也需要額外的技術支援才能將目前已發展健全之低功率電路設計技術完全導入其設計流程中。在前端邏輯單元中，此元件庫挑選出具有較低消耗功率之運算架構單元，並且針對各種組合電路元件發展出一套簡化之最佳化流程。

為了有效降低數位電路之總體功率消耗包含動態功率和靜態功率，大範圍的調降供給電壓為此元件庫環境設計的重點之一。同時，不同臨界電壓之標準元件庫也可進行混用，以利於優化電路要求時序之合成結果。另外，在元件設計流程中依據 power efficient 的電路觀念，在單一晶片設計中運用此元件庫也可分別針對不同操作頻率之模組進行個別的供給電壓的規格支援。

測試電路使用國家晶片中心(CIC)所提供之資源進行晶片下線驗證，根據電路之模擬結果，使用本研究所設計之元件庫進行數位電路合成之通道估測器測試電路可在雙重供給電壓(VCC=1.0V, VCCL=0.6V)下，操作在50 MHz以上，此頻率超過原始IEEE 802.16e所制定之 throughput 標準，並且比原始電路節省趨近於70%之功率消耗。

In modern digital integrated circuit, high performance design with low power dissi-
pation has been accomplished nowadays as the feature size of transistor keeps scaling
down. However, adopting low power techniques to the digital circuit design is crucial
and difficult in engineering practice at current stage. Cell-based flow is the most pop-
ular design flow in the various customized IC design market. Based on these fact, we
proposed a simple cell optimization flow to develop a cell library which enable a low volt-
age operation under 1.0V. Meanwhile, voltage scaling and multi-VCC partitioning low
power technique are also adopted to the modified cell-based design flow. For the isola-
tion between different power domain, the library based macro design is implemented for
the test circuit. By separating power nets into individual voltage block, two independent
regions are provided by each corresponding supply voltages.
According to the simulation results, by using the low voltage library and power
reduction methods merged to the designed flow, a power reduction compared with the
original test circuit approaching 70% can be achieved. Moreover, the test design can
provides two self-defined voltage blocks and voltage scaling options (VCC=1.0V-0.8V;
VCCL=1.0V-0.6V) without any performance degradation.

[1] M. Horowitz, E. Alon, D. Patil, S. Naffziger, R. Kumar, and K. Bernstein, “Scaling, Power, and the Future of CMOS,” in Proc. IEEE International Electron Devices
Meeting (IEDM Technical Digest), Dec. 2005.
[2] N. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J. Hu, M. Irwin, M. Kan-demir, and N. Vijaykrishnan, “Leakage Current: Moores Law Meets Static Power,”
in IEEE Computer, vol. 36, no. 12, pp. 68-57, 2003.
[3] C. Yeh, Y. S. Kang, S. J. Shieh, and J. S. Wang, “Layout Techniques Supporting the Use of Dual Supply Voltages for Cell-Based Designs,” in Proc. DAC, New Orleans, LA, 1999, pp. 62-67.
[4] R. Rao, J. Burns, and R. Brown, “Analysis and Optimization of Enhanced MTC-MOS Scheme,” in Proc. Int. Conf. VLSI Design , 2004, pp. 2790- 2795.
[5] V. Khandelwal and A. Srivastava, “Leakage Control Through Fine-Grained Place-ment and Sizing of Sleep Transistor,” IEEE Trans. Comput.-Aided Des. Integr.
Circuits Syst., vol. 26, no. 7, pp. 1246-1255, Jul. 2007.
[6] K.Usami, N. Kawabe, M. Koizumi, K. Seta and T. Furusawa, “Automated selective multi-threshold design for ultra-low standby applications,” in Proc. International
Symposium on Low Power Electronics and Design, 2002, pp. 202-206.
[7] S. Goel, M. A. Elgamel, M. A. Bayoumi, and Y. Hanafy, “Design Methodologies for High-Performance Noise-Tolerant XOR-XNOR Circuits,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 4, pp. 62-67, Apr. 2006.
[8] A. P. Chandrakasan and R.W. Brodersen (1995). Low Power Digital CMOS Design (1st ed.). Norwell, MA, USA.
[9] N. Zhuang and H. Hu, “A new design of the CMOS full adder,” IEEE J. Solid-State Circuits, vol. 27, no. 5, pp. 840-844, May 1992.
[10] N.Weste and D. Harris (2004). CMOS VLSI Design, A Circuts and Systems Perspective (3nd ed.). Addison-Wesley Longman Publishing Co., Inc.., MA, USA.
[11] M. Vesterbacka, “A 14-transistor CMOS full adder with full voltageswing nodes,” in Proc. IEEE Workshop Signal Processing Systems, Oct. 1999, pp. 713-722.
[12] H. T. Bui, Y. Wang, and Y. Jiang, “Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates,” IEEE Trans. Circuits Syst. II, Analog
Digit. Signal Process., vol. 49, no. 1, pp. 25-30, Jan. 2002.
[13] C. H. Chang, J. Gu, and Mingyan Zhang, “A Review of 0.18-μm Full Adder Performances for Tree Structured Arithmetic Circuits,” IEEE Trans. Very Large
Scale Integr. (VLSI) Syst., vol. 13, pp. 686-695, June 2005.
[14] S. Goel, A. Kumar, and M.A. Bayoumi, “Design of Robust, Energy-Efficient Full
Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 12, pp. 1309-1321, Dec.
2006.
[15] Star-Hspice Manuals, Avanti! Corporation, Fremont, CA. Release 2001.4.
[16] M. Vujkovic and C. Sechen, “Optimized power-delay curve generation for standard cell ICs,” in Proc. Int. Conf. Comput.-Aided Design,, 2002, pp. 387-394.
[17] A. M. Shams, T. K. Darwish, and M. A. Bayoumi, “Performance Analysis of Low-Power 1-Bit CMOS Full Adder Cells,” IEEE Trans. Very Large Scale Integr.
(VLSI) Syst., vol. 10, no. 1, pp. 20-29, Feb. 2002.
[18] B. Zhang, L. Liang, and X. Wang, “A New Level Shifter with Low Power in Multi-Voltage System,” in Proc. 8th International Conference on Solid-State and Integrated Circuit Technology , 2006, pp. 1857-1859.
[19] R. Puri, D. Kung, and L. Stok, “Minimizing Power with Flexible Voltage Islands,” in ISCAS, 2005, pp. 21-24.
[20] 國家晶片系統設計中心. (2003, Oct.). “標準元件庫(Standard Cell Library)概說,” IC Design magazine, pp. 28-36. Available: http://www2.cic.org.tw/information/eNEWS/CICeNews 14.pdf
[21] P. W. Liao, “Evaluation of Advanced Low Power Design Techniques,” M.S. thesis, Dept. Elect. Eng., National Tsing Hua Univ., Hsinchu, Taiwan, July 2007.
[22] Milkyway Environment Data Preparation User Guide, Synopsys Software Inc., Moutain View, CA, USA. Version W-2004.12.
[23] H. Y. Yu, “An Uplink Baseband Processor IP for Mobile MIMO WiMAX Communications,” M.S. thesis, Dept. Elect. Eng., National Tsing Hua Univ., Hsinchu, Taiwan, July 2008.