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研究生: 吳季倫
Wu,Chi-Lun
論文名稱: 應用於音頻系統之三階前饋三角積分調變器
Third-Order Feedforward Sigma-Delta Modulator for Audio Applications
指導教授: 連振炘
Lien,Chenhsin
施君興
Shih,Chun-Hsing
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年: 2008
畢業學年度: 97
語文別: 中文
論文頁數: 100
中文關鍵詞: 超取樣雜訊移頻低失真零點最佳化前饋
外文關鍵詞: Oversampling, Noise-Shaping, Low-Distortion, Zero-Optimization, Feedforward
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  • 在本論文中,針對數位音頻系統的應用,設計出一個低失真三階前饋三角積分調變器。此調變器採用切換式電容電路來實現,屬於離散型的架構,適用於中低速、高解析度的應用上。與傳統的架構做比較,不但減少了一位元DAC回授電路的個數,更適合操作在低電壓的環境中,最後並引入零點最佳化的技術,在調變器之第二級與第三級間加入一條回授路徑,使調變器整體效能得以提升。
    由於高階系統在設計上有穩定度的問題,因此必須使用MATLAB做系統的分析,首先藉由SIMULINK建立調變器理想模型,並針對實體電路的各種非理想效應,加入非理想模型。透過系統的行為模擬,可以找出符合系統性能之電路規格,並以此依據做為實體電路設計上的參考,以縮減HSPICE模擬的時間。此調變器採用台積電0.35um, 2P4M, CMOS製成技術來實現,在訊號頻寬20kHz、取樣頻率5.12MHz的情形下,SNDR可達到86dB且SFDR可達到98dB,另外總功率消耗為2.27mW,晶片面積2.15mm2。經過零點最佳化的修正電路,在不增加額外功率的情況下,晶片面積2.76 mm2,SNDR可提高到91dB且SFDR可達到104dB,約莫15-bit解析度,以符合數位音頻系統的需求。


    In this thesis it designs a low-distortion, third-order feedforward sigma-delta modulator for digital audio system applications. This modulator is realized by switched-capacitor circuits, which belong to the structure of discrete type, and is suitable for low-to-medium, high resolution applications.Comparing it to conventional architecture, this structure not only reduce the numbers of 1-bit DAC feedback circuits, but also is suitable for operating in low-voltage environment. Finally it imports a zero optimization technique, which adds a feedback loop between second and third stage of modulator to increase performance.
    Since the design of high order system may be suffered from stability problem, system simulation by MATLAB is needed. First it builds ideal system model by SIMULINK, and then adds the non-ideal effects to original model in order to find out the corresponding circuit specifications to meet the system performance. As a result the circuits are implemented according to them so it reduces the time of HSPICE simulation. This modulator is implemented in TSMC 0.35um, 2P4M, CMOS technology. With the signal bandwidth of 20kHz and sampling rate of 5.12MHz, it can achieve 86dB SNDR and 98dB SFDR. In addition, the power dissipation is 12.27mW and the chip core size is 2.15mm2. With the zero optimization technique of modified circuit, the chip core size is 2.76mm2 , and it can achieve 91dB SNDR and 104dB SFDR, which about 15-bit resolution, to meet the digital audio application without increasing extra power dissipation.

    第一章 序論 1.1 研究動機……………………………………………………….1 1.2 歷史發展與研究現況………………………………………….1 1.3 論文組織……………………………………………………….2 第二章 三角積分調變器原理 2.1 類比數位轉換器……………………………………………….4 2.1-1量化器…………………………………………………….6 2.1-2效能指標………………………………………………….8 2.1-3奈奎斯特A/D轉換器…………………………………….10 2.1-4超取樣A/D轉換器……………………………………….11 2.1-5三角積分A/D轉換器…………………………………….13 2.2 三角積分調變器……………………………………………….15 2.2-1ㄧ階三角積分調變器……………………………………16 2.2-2二階三角積分調變器……………………………………19 2.2-3高階三角積分調變器……………………………………21 2.2-4調變器架構種類…………………………………………22 2.2-5多位元量化器……………………………………………25 第三章 系統架構分析與行為模擬 3.1 設計流程………………………………………………………26 3.2 低失真架構……………………………………………………27 3.3 系統架構分析…………………………………………………28 3.4 穩定度考量……………………………………………………29 3.5 系統規格………………………………………………………30 3.6 非理想效應……………………………………………………30 3.6-1元件電子雜訊……………………………………………31 3.6-2開關非理想效應…………………………………………34 3.6-3積分器之運算放大器………………………………… 38 3.6-4電容比值不匹配…………………………………………39 3.7 系統架構之行為模擬…………………………………………39 3.8 結論……………………………………………………………47 第四章 電路考量及設計 4.1 切換式電容積分器設計………………………………………49 4.2 運算放大器設計………………………………………………52 4.3 比較器設計……………………………………………………60 4.4 1-bit DAC設計………………………………………………62 4.5 完整Σ-Δ電路設計………………………………………… …63 4.5-1電路詳圖…………………………………………………63 4.2-2時脈分析…………………………………………………66 4.6 時脈產生器設計………………………………………………67 4.7 輸出緩衝器設計………………………………………………68 4.8 電路佈局考量…………………………………………………68 4.9 模擬結果圖……………………………………………………73 第五章 量測考量與結果 5.1 量測裝置………………………………………………………80 5.2 電源調節器電路………………………………………………83 5.3 量測結果與分析………………………………………………85 5.3-1量測結果…………………………………………………85 5.3-2討論分析與結論…………………………………………86 第六章 零點最佳化與效能評估 6.1 系統考量………………………………………………………87 6.2 電路考量………………………………………………………91 6.3 效能評估………………………………………………………94 第七章 結論與未來展望 7.1 結論……………………………………………………………96 7.2 未來展望………………………………………………………96 參考文獻……………………………………………………………98

    [1] 朱穎佳, “三階單迴路ㄧ位元 Σ-Δ ADC的設計與實現,”
    北京清華大學微電子與納電子學系碩士論文,2007.

    [2] I. Fujimori, K. Hamashita, and E. Swanson,“A fifth-order Delta-Sigma modulator with 110 dB audio-band dynamic range,” presented at 93rd Audio Engineering Society Convention, San Francisco, Preprint 3415, Oct. 1992

    [3] R. W. Adams, “Design and implementation of an audio 18 bit using oversampling techniques,"
    Journal of Audio Engineering Society, vol.34, p.153, 1986.

    [4] I. Fujimori, K. Koyama, D. Trager, F. Tam, and L. Longo, “A 5 V Single-Chip Delta-Sigma audio A/D converter with 111 dB dynamic range,”
    IEEE J. Solid-State Circuits, Vol. 32, No. 3, March. 1997.

    [5] M. Dessouky and A. Kaiser,“Very low-voltage digital-audio ΔΣ modulator with 88-dB dynamic range using local switch-bootstrapping,”IEEE J. Solid-State Circuits,vol.36, pp.349–355,Mar.2001.

    [6] Libin Tao, Michiel S. J. Steyaert and Willy Sansen, “A 1-V 140-μW 88-dB Audio Sigma-Delta Modulator in 90-nm CMOS,”IEEE J. Solid-State Circuits, Vol. 39, No. 11, Nov. 2004.

    [7] Silva, P.G.R., Breems, L.J., Makinwa, K.A.A.; Roovers, R., Huijsing, J.H, “An 118dB DR CT IF-to-Baseband ΣΔ Modulator for AM/FM/IBOC Radio Receivers”, ISSCC Dig. Tech. Papers, pp. 66-67, Feb. 2006.

    [8] Lucien J.Breems, Robert H.M. van Veldhoven, Kathleen Philips, Robert Rutten, Gunnar Wetzker, “Continuous-time Sigma-Delta Modulators for Highly Digitised Receivers,” IEEE Philips Research, Eindhoven,The Netherlands, 2006.

    [9] Schoofs, R. and M. Steyaert, “A Design-Optimized Continuous-Time Delta-Sigma ADC for WLAN Applications,” IEEE Transaction on Circuits and Systems, Vol. 54, No. 1, Jan. 2007.

    [10] David Johns and Ken Martin, “Analog Integrated Circuit Design,”Wiley,1997.

    [11] Dr. Hao-Chiao Hong, “Class handout of Advanced analog integrated circuit,”2007.

    [12] Libin Yao,Michiel Steyaert and Willy Sansen, “Low-Power Low-Voltage Sigma- Delta Modulators in Nanometer CMOS,” Published by Springer, Ch.5, 2006.

    [13] Phillip E. Allen and Douglas R. Holberg, “CMOS analog circuit design,” New York, Oxford University Press, 2002.

    [14] Dr. Jieh-Tsorng Wu, “Class handout of Data converter,” 2007.

    [15] Richard Schreier, Gabor C. Temes, “Understanding Delta-Sigma Data converters,” Piscataway, N.J.; Hoboken, N.J.; Chichester: Wiley;, 2005.

    [16] 王ㄧ誠, “利用切換式放大器之低功率雙倍取樣積分三角調變器於生物醫學應用, ” 國立交通大學電機與控制工程研究所碩士論文, 2003.

    [17] J. Silva, U.-K. Moon, J. Steensgaard, and G. C. Temes, Wideband low-distortion delta-sigma ADC topology,”IEEE Electron. Lett., vol. 37, Jun. 2001.

    [18] 楊淳浩, “低失真三角積分調變器之設計與研究,”
    國立清華大學電子工程研究所碩士論文, 2007.

    [19] Ana Rusu and Hannu Tenhunen, “A Third-Order Sigma-Delta Modulator for Dual-Mode Receivers,”
    IEEE International Midwest, Vol 1, Dec. 2003, p68-71.

    [20] 李奇青, “低通三角積分調變器的設計與實現,”
    國立中正大學電機工程研究所碩士論文, 2006.

    [21] Rusu A. and Tenhunen H., “A Third-Order Multibit Sigma-Delta Modulator with Feedforward Signal Path,” IEEE NEWCAS Workshop, 2003, pp. 145-148.

    [22] Piero Malcovati, Simona Brigati, Fabrizio Francesconi, Franco Maloberti, Paolo Cusinato, and Andrea Baschirotto, “Behavior Modeling of Switched-Capacitor Sigma-Delta Modulators,” IEEE Trans. Circuits Systems : Fundamental Theory And Applications, Vol 50, No. 3, Mar. 2003.

    [23] Behzad Razavi., “Design of analog CMOS integrated circuits,” Boston, 2001.

    [24] SD Toolbox, Website:http://www.mathworks.com/matlabcentral/fileexchange.

    [25] Ojas Choksi and L. Richard Carley, “Analysis of Switched-Capacitor Common Mode Feedback Circuit, ” IEEE Transaction on Circuits and Systems, Vol. 50, No. 12, Dec. 2003.

    [26] Zhenyong Zhang and Gabor C. Temes, “A Segmented Data-Weighted-Averaging Technique, ” Digital Object Identifier 10.1109 ISCAS, May 2007.

    [27]Da-Huei Lee and Tai-Haur Kuo, “Advancing Data Weighted Averaging Technique for Multi-Bit Sigma Delta Modulators,” IEEE Transaction on Circuits and Systems, Vol. 54, No. 10, Oct. 2007.

    [28] Khiem Nguyen, Bob Adams, Karl Sweetland, “A 105dB SNR Multibit ΣΔ ADC for Digital Audio Applications, ” IEEE Custom Integrated Circuits Conference 2001.

    [29] 高宗愷, “低電壓三角積分調變器之設計與製作, ”
    國立台灣大學電子工程研究所碩士論文,” 2003.

    [30] J.M. de la Rose, “A CMOS 110-dB @40-kS/s Programmable Gain Chopper- Stabilized Third-Order 2-1 Cascade Sigma-Delta Modulator for Low-Power High-Linearity Automotive Sensor ASICs,” IEEE Journal of Solid-State Circuits, vol. 40, no. 11, Nov 2005

    [31] J.M. Garcia-Gonzalez, “A 0.35um CMOS 17-bit@40kS/s Sensor A/D Interface Based on A Programmable-Gain Cascade 2-1 Modulator,” ISCAS, pp. 205-208, 2004.

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