研究生: |
吳季倫 Wu,Chi-Lun |
---|---|
論文名稱: |
應用於音頻系統之三階前饋三角積分調變器 Third-Order Feedforward Sigma-Delta Modulator for Audio Applications |
指導教授: |
連振炘
Lien,Chenhsin 施君興 Shih,Chun-Hsing |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering |
論文出版年: | 2008 |
畢業學年度: | 97 |
語文別: | 中文 |
論文頁數: | 100 |
中文關鍵詞: | 超取樣 、雜訊移頻 、低失真 、零點最佳化 、前饋 |
外文關鍵詞: | Oversampling, Noise-Shaping, Low-Distortion, Zero-Optimization, Feedforward |
相關次數: | 點閱:2 下載:0 |
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在本論文中,針對數位音頻系統的應用,設計出一個低失真三階前饋三角積分調變器。此調變器採用切換式電容電路來實現,屬於離散型的架構,適用於中低速、高解析度的應用上。與傳統的架構做比較,不但減少了一位元DAC回授電路的個數,更適合操作在低電壓的環境中,最後並引入零點最佳化的技術,在調變器之第二級與第三級間加入一條回授路徑,使調變器整體效能得以提升。
由於高階系統在設計上有穩定度的問題,因此必須使用MATLAB做系統的分析,首先藉由SIMULINK建立調變器理想模型,並針對實體電路的各種非理想效應,加入非理想模型。透過系統的行為模擬,可以找出符合系統性能之電路規格,並以此依據做為實體電路設計上的參考,以縮減HSPICE模擬的時間。此調變器採用台積電0.35um, 2P4M, CMOS製成技術來實現,在訊號頻寬20kHz、取樣頻率5.12MHz的情形下,SNDR可達到86dB且SFDR可達到98dB,另外總功率消耗為2.27mW,晶片面積2.15mm2。經過零點最佳化的修正電路,在不增加額外功率的情況下,晶片面積2.76 mm2,SNDR可提高到91dB且SFDR可達到104dB,約莫15-bit解析度,以符合數位音頻系統的需求。
In this thesis it designs a low-distortion, third-order feedforward sigma-delta modulator for digital audio system applications. This modulator is realized by switched-capacitor circuits, which belong to the structure of discrete type, and is suitable for low-to-medium, high resolution applications.Comparing it to conventional architecture, this structure not only reduce the numbers of 1-bit DAC feedback circuits, but also is suitable for operating in low-voltage environment. Finally it imports a zero optimization technique, which adds a feedback loop between second and third stage of modulator to increase performance.
Since the design of high order system may be suffered from stability problem, system simulation by MATLAB is needed. First it builds ideal system model by SIMULINK, and then adds the non-ideal effects to original model in order to find out the corresponding circuit specifications to meet the system performance. As a result the circuits are implemented according to them so it reduces the time of HSPICE simulation. This modulator is implemented in TSMC 0.35um, 2P4M, CMOS technology. With the signal bandwidth of 20kHz and sampling rate of 5.12MHz, it can achieve 86dB SNDR and 98dB SFDR. In addition, the power dissipation is 12.27mW and the chip core size is 2.15mm2. With the zero optimization technique of modified circuit, the chip core size is 2.76mm2 , and it can achieve 91dB SNDR and 104dB SFDR, which about 15-bit resolution, to meet the digital audio application without increasing extra power dissipation.
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