研究生: |
劉德盛 Liu, Derson |
---|---|
論文名稱: |
運用資料挖礦技術輔助可相互支援機台組間的機台配置決策─以某半導體晶圓製造廠為例 Data mining to support decision making for allocating tools among interchangeable tool sets in semiconductor wafer fabrication |
指導教授: | 劉志明 |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
工學院 - 工業工程與工程管理學系 Department of Industrial Engineering and Engineering Management |
論文出版年: | 2010 |
畢業學年度: | 98 |
語文別: | 中文 |
論文頁數: | 73 |
中文關鍵詞: | 製造週期時間 、在製品存貨 、半導體晶圓製造 、資料挖礦 、決策樹 、倒傳遞類神經網路 |
外文關鍵詞: | cycle time, work-in-process, semiconductor wafer fabrication, data mining, decision tree, back-propagation neural network |
相關次數: | 點閱:3 下載:0 |
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半導體晶圓製造是電子產品供應鏈中的關鍵產業,對於全球經濟有顯著的貢獻。長鞭效應顯示在供應鏈中越上游的產業,其市場需求變化也越大;由於半導體晶圓製造接近電子產品供應鏈的最上游,故半導體晶圓製造承受較大的需求波動。若晶圓製造的週期時間越長,整個電子產品供應鏈的長鞭效應就會益形嚴重。電子產品具有產品生命週期短,且產品多樣化的特性,這些特性會使需求的波動更大。由於長鞭效應加上產品生命週期愈來愈短,半導體晶圓製造必須持續降低製造週期時間,以縮短整個電子產品供應鏈對於需求波動的反應時間。
本研究提出一個資料挖礦方法,運用該方法能相當準確地預測個別機台組的在製品到達速率。其次,根據此預測的在製品到達速率,對可相互支援機台組之間的機台進行適當配置,以輔助可相互支援機台組之機台配置的決策,並顯著地降低製造週期時間。本研究結合決策樹 (decision tree) 與倒傳遞類神經網路 (BPNN: backpropagation neural networks) 的應用來預測個別機台組的在製品到達速率。此外,本研究依據預測的在製品到達速率以及其它歷史輸入變數來建立BPNN模型,可預測個別機台組的在製品存貨水準。資料挖礦的結果顯示,在相同的產量水準下,最佳的機台配置能使可相互支援機台組的總在製品存貨達到最小,也就是使製造週期時間達到最短。本研究並以台灣新竹科學工業園區某晶圓製造廠進行實證研究,以驗證本研究所提方法的效度與效果。
Cycle time reduction is crucial for semiconductor wafer fabrication to maintain competitive advantages. A proper allocation of tools among interchangeable tool sets based on the accurate forecasts for arrival rates of tool sets has significant potential for cycle time reduction.
This study aims to propose a data mining approach to support the decision making for determining the tool allocation among interchangeable tool sets. We proposed a hybrid method that combines the applications of decision tree and back-propagation neural network (BPNN) to forecast the arrival rates of jobs for individual tool sets. In addition, based on the forecasts for arrival rates and other historical input variables, we built BPNN models to predict the work-in-process (WIP) levels of individual tool sets. The results from data mining suggest the tool allocation that can minimize the total WIP of interchangeable tool sets given the same throughput level, i.e. to minimize cycle time of interchangeable tool sets. The proposed approaches were validated via an empirical study in a wafer fab and the results showed practical viability of the propose approach.
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