僅使用標準單元實現之1GHz取樣率的峰值電源電壓落差監測器

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研究生：	徐振翔 Hsu, Chen-Hsiang
論文名稱：	僅使用標準單元實現之1GHz取樣率的峰值電源電壓落差監測器 1 GHz Sampling Rate Worst-Case IR-Drop Monitor using Only Standard Cells
指導教授：	黃錫瑜 Huang, Shi-Yu
口試委員:	呂學坤李昆忠蘇朝琴
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2013
畢業學年度：	101
語文別：	英文
論文頁數：	30
中文關鍵詞：	電源電壓落差、晶片監測、取樣率、最大週期量測、製程校準
外文關鍵詞：	IR-drop, On-Chip Monitoring, Sampling Rate, Maximum Clock Period Measurement, Process Calibration
相關次數：	點閱：2 下載：0
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在三維晶片中，不同的裸晶雖是分別製造，但是整合之後卻是使用同一個外部電源，這個電源經由封裝基座接腳必須以接力的方式，傳播至每一個晶片，由於途中經過一些【穿矽連接孔】，所需驅動的電路也比傳統二維的晶片更多，更容易造成 IR-Drop (電源電壓落差) 的現象。這種現象如果發生的話，輕則造成電路速度拖慢，重則造成錯誤的運算結果發生。因此，三維晶片更加需要有一套隨時監控IR-Drop的機制，以提供三維晶片設計者兩大可以提升可靠度的功能： (1) 驗證【電源網路】的設計無誤， (2) 於嚴重的IR-Drop 問題發生時提供診斷的依據。
電源電壓落差監測技術被用來有效的評估晶片中電源網路的完整性，然而現有的方法無法同時達到高準確性及高取樣率。在本篇論文裡，我們提出了一個創新的方法來解決這個困境。首先，我們的目標由量測電壓波形中的所有取樣點取代為所有取樣點中的峰值電源電壓落差。這項策略可以更容易達到高取樣率的量測。第二，我們採取了週期性的校正機制來考量製程與溫度變異的影響。我們所提出的峰值電源電壓落差監測電路的另一項優點即整體電路僅使用標準單元化(standard cell)來實現。測試晶片經過下線後量測的結果顯示，我們所提出的方法可以支援1GHz以上的取樣率並且達到平均量測誤差3.05mV，最大量測誤差為8.23mV。

IR-drop monitoring has been an effective means to assess the power integrity in real silicon. Existing methods, however, fail to achieve a high accuracy and a high sampling rate simultaneously. In this work, we present a novel method to resolve this dilemma. First of all, we focus on the measurement of the worst-case IR-drop, instead of the entire sampled VDD waveform. This strategy can make a high sampling rate more viable. Secondly, periodic calibration can be supported to account for the process variation and the temperature change if needed. Another benefit of the proposed method is that it can be designed using only standard cells. Test chips have been fabricated and measurement results demonstrate that this method can support a sampling rate of more than 1 GHz, while achieving an average measurement error of 3.05 mV, and a worst-case measurement error of 8.23 mV.

Abstract    i
摘要    ii
致謝    iii
Content    iv
List of Figures    vi
List of Tables    vii
Chapter 1 Introduction    1
1.1 Introduction    1
1.2 Thesis Organization    5
Chapter 2 Preliminaries    6
Chapter 3 Proposed Methodology    8
3.1 Overview    8
3.2 Operation    10
Chapter 4 Monitor Circuit    12
4.1 Architecture of Time-to-Digital Converter    12
4.2 Pipelined Operation    15
Chapter 5 Application to Multiple-Point Monitoring    17
Chapter 6 Experimental Results    20
6.1 Test chip    20
6.2 Analysis of Process Calibration via Simulation    21
6.3 Measurement result for constant VDD voltages    23
6.4 Measurement result for sinusoidal VDD waveforms    24
6.5 Assessment of Temperature Effects    25
6.6 Performance Comparison    26
Chapter 7 Conclusion    28
Bibliography    29

                                

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