本論文研究主要是提出十二位元每秒二百萬次取樣率電流導向式數位/類比轉換器(Current-Steering DAC)。該轉換器利用5+7區段式電流導向式數位/類比轉換器架構方式設計。
本研究採用區段式電流導向式數位/類比轉換器之架構設計，其中5位元的高位元(MSB)為等電流源(Unary Current Cell)，並配合溫度器解碼(Thermometer Code)等電流源的方式來降低差動非線性誤差(Differential Nonlinearity Error)及縮小面積。另外7位元(LSB)部份採用加權二進制電流源(Binary-Weighted Current Cell)。為了使12位元數位輸入訊號的同步與降低突波能量，透過數位門閂(Digital Latch)電路來改善，而在差動開關(Differential Switch)的切換順序，則採用二維距心式之電流源開關切換順序；並為了增加輸出阻抗及提高SFDR，在高、低位元之電流源設計方面，皆採用疊接電流源(Cascode Current Cell)方式設計。
為了達到每秒二百萬次取樣率及1mm2面積設計規格，本研究利用蒙地卡羅
及台積電0.18微米製程設計錦囊，透過不匹配模型(Mismatch-Model)與蒙地卡羅分析法進行設計，再根據Jose Bastos等人所提出最小面積乘積(WL)min，在設計的過程中透過此方法可使設計的電路在電晶體的尺寸縮小有很大的改善，並能夠在良率的提升上有相當大的改善，除此之外設計者能在未做佈局前就能得知，目前所設計的電路是否能滿足在製程變異(Process-Variation)的情況下仍能正常的運作，這對整個晶片的設計流程(Design-Flow)有相當大的助益。
蒙地卡羅模擬結果，以輸入訊號為100MHz且取樣率為200MHz的情況下， DNL及INL分別為0.6LSB及0.8LSB、晶片面積為0.2mm2。該晶片採用TSMC 0.18um 1P6M CMOS 製程來實現。

We propose a 12-Bit 200MS/S Current-Steering DAC based on a Segmented (5+7) current-steering architecture. In order to decrease the differential nonlinearity error (DNL) and reduce area, we employ Unary-Current cell with thermometer code decoder for the 5MSBs and Binary-Weighted Current Cell for the 7LSBs. In order to synchronize inputs and improve glitch energy, we use a digital latch approach. Differential switch order is very critical for DNL, so we use the Two Dimensional Centroid method. In order to enhance DAC output impedance and SFDR, both the MSB and LSB are implemented with Cascode Current Cell.
To meet the 200MS/S and 1mm2 area spec, we perform Monte-Carlo Analysis with TSMC 0.18um Process Design Kit (PDK) and Mismatch Model. Because the Mismatch Model includes Process-Variation information, it can achieve more simulation accuracy than the corner model.
Monte-Carlo simulation result, shows that when the input signal is 100MHz and sample rate is 200MHz, we have DNL=0.6LSB , and INL =0.8LSB. The chip area is 0.2mm2 in a TSMC 0.18um 1P6M CMOS Process.

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