這篇論文提出了一個新穎的功耗模擬技巧，透過預先的描繪與註釋來達到快速又準確的處理器功耗模擬。 追求低功耗已經成為系統晶片設計必要的條件，所以快速且準確的功耗估算對於系統設計來說是相當重要的。然而，由於模擬的模組與功耗模組間相互約束的關係，造成現行的系統層級的處理器功耗估算技巧必須在估算準確度與模擬速度上做取捨。相對的，我們所提出的新穎技巧，在準確度上，採用靜態功耗分析(預先描繪與註釋)，在速度上，則是採取動態功耗計算(執行時模擬)。從實驗結果發現，採用本篇論文所提出的方法可同時達到快速且準確的功耗模擬，速度上可超過每秒兩億個指令，準確度與閘極層級的功耗模擬器相比誤差在百分之三以內。

This paper proposes a novel power simulation technique utilizing pre-characterization and annotation to achieve fast and accurate processor power simulation. Since low power consumption has become a default requirement for system-on-chip (SOC) designs, fast and accurate power estimation is essential for system designs. However, constrained by tight coupled simulation and power models, current system-level processor power estimation techniques have to compromise estimation accuracy for simulation speed. In contrast, our proposed novel technique performs static power analysis (pre-characterization and annotation) for accuracy and then dynamic power calculation (runtime simulation) for speed. The experimental results show that the proposed approach can achieve both high efficiency (more than 200 MIPS) and high accuracy, within 3 % error rate compared with gate-level power simulation.

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