H.264視訊解碼耗能分析與降低｜國立清華大學博碩士論文庫

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研究生：	洪維成 Wei-cheng Hung
論文名稱：	H.264視訊解碼耗能分析與降低 Power Analysis and Reduction of an H.264/AVC Video Decoder System
指導教授：	林永隆 Youn-long Lin
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2007
畢業學年度：	95
語文別：	英文
論文頁數：	32
中文關鍵詞：	H.264 、影像壓縮、功耗
外文關鍵詞：	H.264/AVC, power consumption, video compression
相關次數：	點閱：2 下載：0
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隨著半導體製程的進步，耗能問題不只是像過去被輕忽，被遺忘的問題。如何降低耗能將益趨重要，尤其是如視訊解碼之類的資料密集相關應用。由國際組織ITU-T 及ISO共同提出的H.264/AVC，正是目前最先進的視訊解碼器，在低資料傳輸率下可提供比先前標準更高畫質的影像。我們實驗室已經開發出一個全硬體化支援H.264/AVC 主要檔次的視訊解碼器。在此論文中，先分析整體總耗能，評估出耗費大量功耗原因後，對症下藥，提出一些節省耗能的新方法如H.264特有的略過模式，以及針對時序耗能、靜態隨機處理記憶體耗能，採用現有的方法來大量降低此系統的耗能，並且更進一步評估每種方法的有效程度。除了總耗能外，我們亦針對尖峰功率，重新安排每個解碼工具執行時間，儘可能地錯開關鍵性的解碼工具執行時段來大幅降低尖峰功率，使此解碼系統更穩定且更可靠。在不影響解碼器執行效能下，將上述提出來的方法應用到此系統之後，可以跑在三十百萬赫茲(30 MHz)，達到即時解碼(每秒至少三十張畫面)標準畫質(720x480)大小的影像，而消耗總耗能達21.2mW，耗費尖峰功率達330mW。結果和原本作品相較之下，分別可以省下大約百分之五十三的總耗能和百分之四十五的尖峰功率。當畫面延伸至高畫質(HDTV)解析度時，和其他先前作品比較之下，我們仍然可以節省約百分之三到百分之四十六的耗能。

As semiconductor technology advances, energy efficiency becomes important, especially for data-intensive applications like video codec. We have designed a hardwired H.264/AVC main profile decoder system. We propose several techniques together with some well-know power-saving methods to reduce the total energy and peak power. After appling these techniques, our decoder can real-time decode D2 (720x480) video sequences consuming 21.2 mW of average power and 330 mW of peak power.

Contents
ABSTRACT    1
CONTENTS    2
LIST OF FIGURES    3
LIST OF TABLES    4
CHAPTER 1    5
INTRODUCTION    5
1.1 THE OVERVIEW OF H.264/AVC    5
1.2 NTHU H.264/AVC DECODER SYSTEM    6
1.3 LOW POWER TECHNOLOGY    7
CHAPTER 2    9
PREVIOUS WORK    9
2.1 RELATED WORK    9
2.2 EXISTING POWER-SAVING TECHNIQUES    12
CHAPTER 3    14
POWER ANALYSIS OF AN H.264/AVC DECODER SYSTEM    14
3.1 POWER DISTRIBUTION    14
3.2 TOTAL ENERGY FOR DECODING AN MB    16
3.3 PEAK POWER OF EACH MB    17
CHAPTER 4    18
POWER REDUCTION TECHNIQUES FOR THE DECODER SYSTEM    18
4.1 TOTAL ENERGY REDUCTION    18
4.1.1 Clock Power Reduction    18
4.1.2 Memory Power Reduction    20
4.1.3 Skip Mode for Power Reduction    22
CHAPTER 5    27
EXPERIMENTAL RESULTS    27
CHAPTER 6    30
CONCLUSION    30
BIBLIOGRAPHY    31


List of Figures
Figure 1. The NTHU H.264/AVC Decoder Block Diagram    6
Figure 2. Types of Clock Gating    13
Figure 3. Decoder Power Distribution    14
Figure 4. The Power Consumption of Each Functional Block    15
Figure 5. Max, Average, and Min Number of Cycles to Decode a MB    16
Figure 6. Peak Power of Decoding an MB    17
Figure 7. The Module-based Clock Gating for Our Decoder    19
Figure 8. Three-layer Memory Hierarchy    21
Figure 9. Memory Partition and Selector    22
Figure 10. Active Period Cycles Prediction for Each MB    24
Figure 11. The Flow Chart of Active Period Rescheduling    25
Figure 12. A Example of Active Period Rescheduling    26
Figure 13. Power Reduction due to Clock Gating in Intra-frame    27

List of Tables
Table 1. The Comparison of Previous Work    11
Table 2. ENABLE Signals    19
Table 3. Memory Characteristics    20
Table 4. The Memory Power Reduction in Our Decoder    28
Table 5. The Results of PAPC and Peak Power    29

                                

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[13]. PrimePower, Synopsys Corporation http://www.synopsys.com/products/power/primepower_ds.pdf

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