本篇論文提出一新穎以梯形閘極氧化層結構的反熔絲記憶元件(Step Gate Oxide Anti-Fuse, SGAF)，此記憶元件可內嵌於一般標準邏輯製程製作之晶片。利用光罩定義在同一閘極上形成厚薄氧化層而成梯形狀，並使用硬崩潰作為單次寫入型之機制，利用淺溝渠(Shallow Trench Isolation)可以避免未寫入記憶元受到貫穿電壓影響，隔離元件之間漏電流干擾。藉特殊元件佈局技巧及薄氧化層比例設計，可以增大電場效應，提升寫入資料速度。SGAF 記憶元件在高電壓寫入時低於4V，可避免大部份非揮發性記憶元件使用的高電壓，所造成的高功率損耗的缺失。元件陣列則採用NOR 型式陣列，並加入字元線選擇電晶體(select transistor)以降低超薄閘極漏電流干擾寫入及讀取情況，提高記憶元件可靠度。
此新穎之梯形閘極反熔絲SGAF 記憶元件驗證於90nm 和65nm 標準邏輯製程，經晶片量測結果顯示，1Kbits 陣列之記憶元件電流分佈，提供足夠的讀取電流差距，達成資料的存取。

In this study, a novel logic One-Time-Programmable (OTP) cell using Step Gate Oxide of Anti-Fuse (SGAF) with fast programming was demonstrated by nano-meter CMOS logic processes for advance logic NVM’s applications. The silicon data has proven that this cell can be adapted in both 90nm & 65nm technology nodes. The SGAF cell features complete compatibility to logic process without any
additional change in process or mask layers. Gate oxide rupture is used as programming mechanism for the SGAF memory cell. The unique design in this cell is creating a oxide thickness difference in this step gate oxide formation. This cell can be programmed under 4V within 10us, while this low programming voltage can greatly
reduce the power consumption as well as complexity in the peripheral circuits.
As the breakdown of gate oxide is used as the programming method in SGAF array memory cell, this device is expected to scale better in advance technologies.

[1] John P.Uyemura, “Introduction to VLSI Circuits and System”
[2] Joe E. Brewer and Manzur Gill,”Nonvolatile Memory Technologies with Emphasis on Flash : a Comprehensive Guide to Understanding and Using NVM Devices,” 2008 published by IEEE Press Series on Microelectronic Systems.
[3] Robert S.C. Wang, Rick S. J. Shen and Charles C. H. Hsu, “ Neobit@- High Reliable Logic Non-Volatile Memory (NVM)” Int. Physics Failure and Analysis of Integrated Circuit., 2004, pp. 111-114
[4] Tadahiko Horiuchi,“Storage and recovery of data based on change in MIS transistor characteristics ”US Patent#US 7,149,104 B1, Dec.12,2006.
[5] C. Kothandaraman, et al., "Electrically Programmable Fuse (eFUSE) Using Electromigration in Silicides" Elec. Dev. Lett. 23, 2002, pp.523-525.
[6] Feng Li, Xiaoyu Yang, Albert T. Meeks, James T. Shearer, and Kim Yen Le, ”Evaluation of SiO2 Antifuse in a 3D-OTP Memory, ” IEEE Transactions on device and materials reliability, vol. 4, No. 3, Sep. 2004.
[7] J. Peng, G.. Rosendalem, M. Fliesler, D. Fong, J. Wang, C. Ng, Z.Liu, and H.Luan,, “NVM A Novel Embedded OTP NVM Using Standard Foundry CMOS Logic Technology, ” Non-volatile Semiconductor Memory Workshop., 2006, pp. 24-26.
[8] M. Lenzinger and E. H. Snow, “Fowler-Nordheim Tunneling into thermally Grown SiO2,” Jpn. J. Appl. Phys., Vol. 40, 1969. pp. 278-283,
[9] Y-C Yeo,T-J King and C.M. Hu,”MOSFET Gate leakage modeling and selection guide for alternative gate dielectrics based on leakage considerations,” IEEE Trans.
on Electron Devices, Vol. 50, April 2003, pp. 1027-1035.
[10] Dieter K.Schroder,” Semiconductor Material and Device Characterization,”3th edition, published by A John Wiley & SONS., INC.
[11] J.W. McPherson and D.A. Baglee,” Acceleration Factors for Thin Gate Oxide Stressing,” Annual Int. Reliability Physics Symp., 1985, pp. 1-5.
[12] K.P. Cheung,” A physics-based, unified gate-oxide breakdown model.” Int. Electron Devices Meeting Tech., 1999, pp. 719-723.
[13] J.W. Mcpherson, H.C. Mogual,” Disturb bounding states in SiO2 thin films & their impact on time –dependent dielectric breakdown.” Annual Int. Reliability
Physics Symp., 1998, pp. 47-56.
[14] Dwight L. Crook,” Method of determining reliability screens for time dependent dielectric breakdown,” Annual Int. Reliability Physics Symp., 1979, pp. 1-7.
[15] Cheng T. Want, editor. Hot Carrier Design Considerations for MOS Devices and Circuits. Van Nostrand Reinhold, 1992.
[16] IBM J.RES & DEV by J. H. Stathis.
[17] Michel Depas, Tanya Nigam, and Marc M. Heyns.” Soft Breakdown of Ultra-Thin Gate Oxide Layers.” IEEE Transactions on Electron Devices, vol. 43, No. 9, Sep. 1996. pp. 1499-1504.
[18] B. Kaczer, A. De Keersgieter, S. Mahmood’, R. Degraeve, G. Groeseneken.”Impact of gate-oxide breakdown of varying hardness on narrow and wide nFET's.” IEEE Annual International Reliability Physim Symposium, Phoenix.
2004. pp. 79-83.
[19] Lei Jun Tang, Kin Leong Pey, Chih Hang Tung, M. K. Radhakrishnan, and Wen He Lin.“Gate dielectric breakdown induced microstructural damage in MOSFETs.” IEEE Transactions on device and materials reliability, vol. 4, No. 1, March 2004. pp. 38-45.
[20] Thayalan A. L. Selvarajoo, Rakesh Ranjan, Kin-Leong Pey, Lei-Jun Tang, Chih Hang Tung, and Wenhe Lin.” Dielectric-Breakdown-Induced Epitaxy: A Universal Breakdown Defect in Ultrathin Gate Dielectrics”. IEEE Transactions on Tevice and Materials Reliability, Vol. 5, No. 2, June 2005. pp. 109-197.
[21] H. C. Lin, D . Y. Lee, C. Y. Lee, T. S. Chao, T. Y. Huang, nd T. Wang.” New Insights into Breakdown Modes and Their Evolution in Ultra-Thin Gate Oxide.”VLSI Technology, Systems, and Applications, 2001.pp. 37-40.
[22] Chih-Hang Tung, Kin-Leong Pey, L. J. Tang, Y. Cao, M. K. Radhakrishnan, and W. H. Lin.”Fundamental narrow MOSFET gate dielectric breakdown behaviors and their impacts on device performance.” IEEE Transactions on Electron Devices,
vol. 52, No. 4, April 2005. pp.473-482.
[23] L.J Tang, K.L. Peg, C.H. Tung, M.K Radhakrishnan and W.H. Lin. “Gate dielectric breakdown induced micro-structural damages in MOSFETs.”Int. Physical and Failure Analysis of Integrated Circuits, 2003. pp. 134-140
[24] K.L Pey. R. Ranjan, C.H. Tung, L.J. Tang, W.H. Lin and M.K. Radhakrihnan. ”Gate dielectric degradation mechanism associated with DBIE evolution.” IEEE Annual International Reliability Physim Symposium, Phoenix. 2004. pp. 117-121.
[25] Piero Olivo, Thao N. Nguyen, and Bruno ricco.“High file induced degradation in ultra-thin SiO2 films.”, IEEE Transactions on Electron Devices, vol. 35, No. 12, April 1988. pp. 2259-2267.
[26] Felice Crupi, Ben Kaczer, Robin Degraeve, An De Keersgieter, and Guido Groeseneken. ”A comparative study of the oxide breakdown in short-channel nMOSFETs and pMOSFETs stressed in inversion and in accumulation regimes.”IEEE Transations On Device and Materials Reliability, vol. 3, No. 1, March 2003. pp.8-13.
[27] Ih-Chin Chen, Holland, S.E., Chenming Hu, “Electrical Breakdown in Thin Gate and Tunneling Oxides,” Solid-State Circuits, IEEE Journal of Feb 1985, pp. 333-342.
[28] Jack C.Lee, Ih-Chin Chen and Chenming Hu, “Modeling and Characterization of Gate Oxide Reliability”, Electron Devices, IEEE Transactions., 1988, pp.2268-2278.
[29] Koji Eriguchia and Masaaki Niwa,”Temperature and stress polarity-dependent dielectric breakdown in ultrathin gate oxides,” Appl. Phys. Lett.,, Vol. 73, No. 14, 5 October 1998
[30] C.-C. Chen, C.-Y. Chang, C.-H. Chien, and T.-Y. Huang,”Temperatureaccelerated dielectric breakdown in ultrathin gate oxides,” Appl. Phys. Lett.,, Vol. 74, No. 24, 14 June 1999.
[31] Nigam, T. Degraeve, R. Groeseneken, G. Heyns, M.M. Maes, H.E.,“Constant current charge-to-breakdown: Still a valid tool to study the reliability of MOS structures.” Annual Int. Reliability Physics Symp., 31 Mar-2 Apr 1998, pp 62-69.
[32] Young Hee Kim Onishi, K. Chang Seok Kang Hag-Ju Cho Nieh, R. Gopalan, S. Choi, R. Jeong Han Krishnan, S. Lee, J.C., “Area dependence of TDDB characteristics for HfO2 gate dielectrics” IEEE Electron Device Lett.,Vol.
23 ,no.10.11. Oct 2002, pp.594- 596.
[33] K. Ohgata, M. Ogasawara, K. Shiga, S. Tsujikawa, E. Murakami, H. Kato, H. Umeda and K. Kubota,” Universality of Power-Law Voltage dependence for TDDB lifetime in Thin Gate Oxide PMOSFETs” Annual Int. Reliability Physics
Symp., 2005, pp.372-376.
[34] A. Haggag, N. Liu, D. Menke, M. Moosa, “Physical model for the power-law voltage and current acceleration of TDDB.” Microelectronics Reliability 45 ., 2005, pp. 1855–1860.
[35] Rainer. Duschl, Rolf. Peter Vollertsen, ”Is the power law model applicable beyond the direct tunneling regime.” Microelectronics Reliability 45.,2005, pp.1861–1867.
[36] A. Kerber, M. Röhner, T. Pompl, R. Duschl, M. Kerber, “Liftime prediction for CMOS device base on progressive breakdown.” Annual Int. Reliability Physics Symp., 2007, pp.217-220.
[37] Eugene S. Anolick, Glenn R. Nelson, “Low Field Time Dependent Dielectric Integrity,” Annual Int. Reliability Physics Symp., 1979, pp. 8-12.
[38] Felice Crupi, Ben Kaczer, and Guido Groeseneken. New insights into the relation between channel hot carrier degradation and oxide breakdown in short channel nMOSFETs. IEEE Electron Device Letters, 24(4): 278–280, April 2003.