隨著製程技術的演進，為了使電路擁有更好的效能，非同步電路被提出使用。不須使用時脈訊號的非同步電路，由於是資料驅動的緣故，使延遲時間不同於同步電路的運行時間取決於最長路徑的延遲，而是注重於平均延遲。然後非同步電路的設計，包含使用商業電腦輔助設計軟體，對於設計者而言，需要付出較多心力去設計。為了讓使用者能使用同步合成工具來處理非同步電路，同步合成工具在時間最佳化上需要進一步處理。
為了得知在電路中，對哪一個邏輯閘增進驅動能力有最好的效果，本論文使用事件驅動模擬來模擬出組合電路的平均延遲以及各個邏輯閘的轉態機率，來求得邏輯閘的敏感度。然而，傳統的事件驅動模擬隨著輸入訊號數目的增加，模擬時間也耗費更久。為了減少事件驅動模擬的時間，本論文提出以超級閘來分割電路後，對每個超級閘執行事件模擬驅動後，得到超級閘不同輸入樣式的最差延遲與和輸出結果。最後再對分割後的電路進行事件模擬，得到電路的平均延遲。

Asynchronous circuits, which require not global clock signal, may have the advantages of lower power consumption, better tolerance to device variations, better circuit modularity and easier reuse. Thus, asynchronous circuit has been revisited by many research groups for the adoption in circuit design with advanced semiconductor technologies. Since no synchronization is needed, data are processed as they become available; when the results are available they are fed to the next stage as soon as possible. As a result, the asynchronous circuit can achieve average-delay performance, in order to further optimize asynchronous circuits performance, the average delay needs to be calculated efficiently. It is the ultimate goal of this research to find an effective way for asynchronous circuit optimization.
As the first step, this thesis studies and proposes ways to find the average-case delay which is given digital combination circuit blocks. The event-driven approach can simulate the digital circuit accurately and thus produce the average delay reliably. However, as the number of gates increases, the simulation time can be extensive. Using probabilistic signal propagation, it is possible to calculate the average delay systematically. However, when there are reconvergent fanout paths in the circuit, this probabilistic approach becomes quite complicated, and may produce inaccurate results or take a long time for detailed simulations. This thesis proposes to group the gates around the reconvergence paths to form supergates, and create necessary circuit modules for these supergates such that they can be simulated in the same way as a primitive gate. Thus, significant saving in simulation time and more accurate average delay time can be obtained.
To be compatible to the existing commercial tools, circuit description in Standard Delay Format (SDF) is processed and a reliable event-driven simulator has been implemented. Using this event-driven simulator with the supergate capability, the next step of asynchronous circuit optimization may be carried out in the near future.

[1]
Hauck, S., “Asynchronous design methodologies: an overview,” in Proc. IEEE , vol.83, no.1, Jan 1995, pp.69,93
[2]
S. Y. Yeh, “An Asynchronous CircuitFroont-end Design Flow with Synchronous
CAD Tools,” M.S. thesis, Department of Electrical Engineering, National Tsing Hua University, Hsinchu, 2011
[3]
S. C. Seth and V. D. Agrawal, “A new model for computation of probabilistic testability in combinational circuits”, Integration, the VLSI Journal, vol. 7, pp. 49-75, 1989
[4]
Min, H.B.; Park, E.S., “Graph-theoretic algorithm for finding maximal supergates in combinational logic circuits,” in Proc. IEE, Circuits, Devices and Systems, vol. 143, no. 6, pp. 313– 318, 1996
[5]
AHO, A.V., HOPCROFT, J.E., ULLMAN, J.D., The design and analysis of computer algorithms, Addison-Wesley Publishing Company, Reading, Massachusetts, pp. 179-187, 1974
[6]
SETH, S.C., PAN, L., and AGRAWAL, V.D., “PREDICT - Probabilistic estimation of digital circuit reliability,” in Proc. of the International Fault Tolerant computing Symposium, pp. 220-225, June 1985
[7]
Cheoljoo Jeong; Nowick, S.M., "Technology Mapping and Cell Merger for Asynchronous Threshold Networks," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.27, no.4, pp.659,672, April 2008
[8]
Beerel, P.A.; Yun, K.Y.; Wei-Chun Chou, "Optimizing average-case delay in technology mapping of burst-mode circuits," in Proc. of the International Symp. on Advanced Research in Asynchronous Circuits and Syst., pp. 244–259, 1996
[9]
Fant, K.M.; Brandt, S.A., "NULL Convention LogicTM: a complete and consistent logic for asynchronous digital circuit synthesis," in Proc. of International Conference on Application-Specific Systems, Architectures and Processors (ASAP '96), pp. 261-273, 1996
[10]
Sacker, M.; Brown, A.D.; Rushton, A.J.; Wilson, P.R., "A behavioral synthesis system for asynchronous circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.12, no.9, pp. 978, 994, Sept. 2004
[11]
Dusung Kim; Ciesielski, M.; Seiyang Yang, “A new distributed event-driven gate-level HDL simulation by accurate prediction,” in Proc. of Design, Automation, and Test in Europe Conference & Exhibition (DATE), pp. 547-550, 2011
[12]
D. Kim et al., “Temporal Parallel Simulation: A Fast Gate-Level HDL Simulation using Higher Level Models,” in Proc. IEEE Design, Automation and Test in Europe (DATE 11), pp. 1584-1589, 2011
[13]
A. Ghosh, S. Devadas, K. Keutzer, and J. White, “Estimation of average switching activity in combinational and sequential circuits,” in Proc. 29th Design Automation Conference, pp. 253-259, June 1992
[14]
Quine, W. V., "The Problem of Simplifying Truth Functions". The American Mathematical Monthly 59, 8, Oct. 1952, 521–531
[15]
Quine, W. V., "A Way to Simplify Truth Functions". The American Mathematical Monthly 62, 9: 627–631
[16]
McCluskey, E.J., Jr., "Minimization of Boolean Functions". Bell System Technical Journal 35, 6: 1417–1444
[17]
Peter M. Maurer, “Multi-Delay Simulation,” available at: http://cs.baylor.edu/~maurer/aida/desauto/chapter4.pdf