我們在這篇論文中提出一個用於先進視訊壓縮法的矽智產原型。我們的設計方法包含矽智產設計及系統整合的流程。基於不同的驗證目標，我們使用數個研發平台。我們使用該設計方法在ARM平台上整合成功，並且討論我們的實作成果。本硬體核心包含了六個矽智產，每個矽智產是由一位碩士生負責。該硬體核心平均最多需要768個周期來解碼一個巨集區塊。

We propose an IP-based prototype for H.264 main profile decoding. Our design methodology consists of not only IP-level but also system-level design flow. We use several SOC development environments for different verification purposes. We also describe our implementation result on an ARM platform using the proposed methodology. The hardware core consists of 6 IP blocks, each implemented by a fellow master student. Its average performance is better than 768 cycles/MB.

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