分析模型對評估最大串音雜訊和找出相關圖樣在多條線上

簡易檢索 / 詳目顯示

回結果列表

研究生：	張宏瑋 Hung-Wei Chang
論文名稱：	分析模型對評估最大串音雜訊和找出相關圖樣在多條線上 Analytic Models for Estimating Worst Case Crosstalk Noise and Finding Corresponding Patterns on Multiple Lines
指導教授：	張慶元 Tsin-Yuan Chang
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2005
畢業學年度：	93
語文別：	英文
論文頁數：	48
中文關鍵詞：	串音雜訊、圖樣
外文關鍵詞：	crosstalk, pattern
相關次數：	點閱：3 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

由於製程快速演進，元件的大小隨之快速縮小，網路(interconnect)相關的操作問題已經變的引人注意，這主要是由於增加的RC延遲和串音雜訊(crosstalk noise)的存在，這些寄生的效應也許會遏止先進製程技術的好處。先進製程包含增加金屬的層數、較窄的金屬線寬、線和線之間的距離越來越短等等，這些效應都會造成主要產生串音雜訊(crosstalk noise)的Coupling Capacitance變的越來越大。本論文目的即提供一個評估最大串音雜訊跟它在何時發生及何種相關的輸入圖樣可以激發此雜訊的分析方法，而且分析時間跟HSPICE比較起來會快很多。
前人所提出的方法皆用簡單的模型去模擬線前端Driver的部分，本篇論文提出了有效率的模型去模擬此部分，藉著將Aggressor及Victim的Driver內的輸出電阻用分段及電壓相關模型去套用，使在分析時精確度增加不少，且使用Superposition by Two Lines Structure的方法來降低分析多條線的複雜度，並藉由Dominant-Pole Truncation Approximation來計算轉移函數，使計算轉移函數的時間大大降低。
所有的例子分別使用提出的方法模擬和HSPICE模擬並針對結果加以比較，在比較之後發現提出的方法比用HSPICE軟體模擬快將近一百倍，且其最大串音雜訊及發生時間誤差分別為小於10%和小於10ps，比以往方法的準確度高出許多，並且所生出的測試圖樣也確實有將串音雜訊變大的功用。
之後也許可以考慮電感元件和電感耦合的效應，不過這一部分需用Transmission Line的理論去做分析，而並非再以單純的轉移函數計算，也可以往串音雜訊對延遲所產生的效應這方面去做。

An analytical method for estimating crosstalk noise peak time, peak value and the corresponding worst case noise (WCN) pattern is proposed in this thesis. Based on the transfer function from aggressor line to victim line, the peak crosstalk noise (Vpeak), peak crosstalk noise time (Tpeak) on the victim line which is attacked by aggressor line can be found. Different from past modeling method, the driver of aggressor line and the driver output resistance of victim line are, respectively, replaced with segmental RC model and voltage dependent model for more accuracy. Compare with Spice simulations, the results obtained by proposed method are close, but execution time is much shorter in 1-2 order. With worst case noise (WCN) patterns for aggressor lines, maximum crosstalk noise on victim line can be found.

Contents
Abstract    1
Contents    2
List of Figures    4
List of Tables    6
Chapter 1 Introduction    7
1.1    Crosstalk Phenomena    8
1.2    Motivation    9
1.3    Organization      10
Chapter 2 Preliminaries    11
2.1    Gate Modeling    11
2.1.1    Inverter Gate Model    11
2.1.2    Analysis of Parameters    13
2.2    Victim Line’s Output Resistance MOdeling    16
2.2.1    Linear Steady State Resistance Model    16
2.2.2    Voltage Dependent Model    17
2.3    Worst-Case Crosstalk Noise (WCN)    19
2.3.1    The WCN Condition    19
2.3.2    Aggressor Alignment    20
Chapter 3 The Proposed Analysis Flow    21
3.1    Analysis Transfer Function    21
3.1.1    Input Signal Information    23
3.1.2    RC Model of Line Structure    24
3.1.3    Line Structure Combine with Inverter Model    25
3.1.4    Superposition by Two Lines Interconnect Structure    26
3.1.5   Segmental RC Model and Voltage Dependent Model
       for Generating Transfer Function    28
3.2    Estimate Peak Value and Peak Time    32
3.2.1    Function of Peak Value and Peak Time    32
3.2.2    The Method to Find Real Peak Value and Peak Time    33
3.3    Aggressor Alignment    36
Chapter 4    Simulation Results and Comparisons    38
4.1    Simulation Cases    38
4.2    Simulation Results    39
4.2.1    Change Line R    39
4.2.2    Change Line to Ground C    40
4.2.3    Change Time Constant of Input Exponential Signal    42
4.2.4    WCN Pattern    43
4.2.5    Speedup Factor    45
Chapter 5 Conclusions    46
Bibliography    47

 List of Figures
Fig. 1.1 Crosstalk Noise Produced by Coupling Capacitance    8
Fig. 2.1 Inverter Model    12
Fig. 2.2 Output Resistance Curve    13
Fig. 2.3 Output Capacitance Curve    14
Fig. 2.4 Approximated Vout Signal v.s. Real Vout Signal    15
Fig. 2.5 Modeled Resistances    17
Fig. 2.6 The WCN Condition    19
Fig. 2.7 Aggressor alignment    20
Fig. 3.1 The Proposed Analyzing Flow    22
Fig. 3.2 Exponential Input Waveform    23
Fig. 3.3(A) Lumped RC Model    24
Fig. 3.3(B) π Model    24
Fig. 3.3(C) 4π Model       24
Fig. 3.3(D) Distributed RC Model    24
Fig. 3.4 Line Structure Combine with Inverter Model    25
Fig. 3.5 Example of 1v3a    26
Fig. 3.6 Interconnect Structure of Two Line    27
Fig. 3.7 Divisions of Input Signal    29
Fig. 3.8 Segmental Output Resistance    30
Fig. 3.9 Average the Rout of Each Segment    30
Fig. 3.10 Flow of Generating Transfer Function    31
Fig. 3.11 Flow to find the real peak value and peak time    35
Fig. 3.12 The Phenomenon of Finding Real Peak Time    35
Fig. 3.13 Flow of WCN Pattern Generation    36
Fig. 3.14 Example of Three Lines Result    37

Fig. 4.1 The Parameters of Simulation    38
Fig. 4.2 Plot Simulation Results of Changing Line R    40
Fig. 4.3 Plot Simulation Results of Changing Line to Ground C    41
Fig. 4.4 Plot Simulation Results of Changing Time Constant    43
Fig. 4.5 Plot Simulation Results of WCN    44
Fig. 4.6 Run Time of Tool and SPICE    45
Fig. 4.7 Speedup Factor    45

List of Tables
Table 4.1 Simulation Results of Changing Line R    39
Table 4.2 Simulation Results of Changing Line to Ground C    41
Table 4.3 Simulation Results of Changing Time Constant    42
Table 4.4 Simulation Results of Changing Input Signal of Five Lines    44

                                

[1] Shabbir Batterywala, and Narendra Shenoy, “Computing Silent Gate Models for Noise Analysis from slew and Delay Tables”, Proc. of the 17th International Conference on VLSI Design, 2004, pp. 989-994
[2] Junmou Zhang and Eby G. Friedman, “Effect of Shield Insertion on Reducing Crosstalk Noise between Coupled Interconnects”, Proc. of the 2004 International Symposium on volume 2, 23-26 May 2004, pp. 529-32 vol.2
[3] L. H. Chen and M. Marek-Sadowska, “Aggressor alignment for worst-case crosstalk noise,” IEEE Transactions on Computer-Aided Design, vol. 20, no. 5, pp. 612-621, May 2001.
[4] A. Nabavi-Lishi and N. C. Rumin, “Inverter Models of CMOS Gates for Supply Current and Delay Evaluation”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 10, Oct. 1994, pp. 1271-1279.
[5] J. Chen and L. He, “Determination of Worst-Case Crosstalk Noise for Non-Switching Victims in GHz+ Interconnects”, IEEE Design Automation Conference, Proceedings of the ASP-DAC, Asia and South Pacific, Jan. 2003, pp. 162-167.
[6] C. Werner, R. Gottsche, A. Worner and U. Ramacher, “Crosstalk noise in future digital CMOS circuits,” Design, in Proceedings of IEEE Design Automation and Test in Europe Conference and Exhibition, pp 331-335, 2001.
[7] F. Dartu, N. Menezes, and L. T. Pileggi, “Performance Computation of Precharacterized CMOS Gate with RC Loads”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no.5, May, 1996, pp. 544-553.
[8] A. Chatzigeorgiou, S. Nikolaidis, and I. Tsoukals, “Modeling CMOS Gates Driving RC Interconnect Loads”, IEEE Transactions on Circuit and Systems II – Analog and Digital Signal Processing, vol. 48, no. 4, Apr. 2001, pp. 413-418.
[9] P. Renault, P. Bazargan-Sabet, and D. L. Du, “A MOS Transistor Model for Peak Voltage Calculation of Crosstalk Noise”, Proceeding of IEEE on Electronics, Circuits and Systems, 9th International Conference, vol. 2 , Sept. 2002, pp. 773 – 776.
[10] J. Cong, D. Z. Pan, and P. V. Srinivas, “Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization”, Proceedings of the IEEE Asia South Pacific Design Automation Conference, January 2001, pp. 373-378
[11] F. Caignet, S. Delmas-Ben Diaz, and E. Sicard, “On the Measurement of Crosstalk in Integrated Circuits”, IEEE Transactions on Very Large Scale Integration Systems, vol. 8, no. 5, Oct. 2000, pp. 606-609.
[12] K. T. Tang, and E. G. Friedman, “Interconnect Coupling Noise in CMOS VLSI Circuits”, Proc. Intl. Symp on Physical Design, 1999, pp. 48-53.

全文公開日期本全文未授權公開 (校內網路)
全文公開日期本全文未授權公開 (校外網路)

簡易檢索 / 詳目顯示

相關論文