使用數位誤差修正之迴圈式類比數位轉換器｜國立清華大學博碩士論文庫

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研究生：	陳明志 Ming-Jr Chen
論文名稱：	使用數位誤差修正之迴圈式類比數位轉換器 Cyclic ADC using Digital Error Correction technique
指導教授：	黃惠良 Huey-Liang Hwang 楊武智 Wu-Zhi Yang
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 產業研發碩士積體電路設計專班 Industrial Technology R&D Master Program on IC Design
論文出版年：	2007
畢業學年度：	95
語文別：	英文
論文頁數：	51
中文關鍵詞：	迴圈式類比數位轉換器、數位錯誤更正、乘法式數位類比轉換器
外文關鍵詞：	Cyclic ADC, Digital Error Correction, MDAC
相關次數：	點閱：4 下載：0
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近來,攜帶式的電子產品設備顯示器常以電阻列陣式作為手寫輸入。在最近的發展裡,光感應列陣能夠成功地埋置在面板中並且捕獲通過面板的影像是可實行的。在這次研究中, 我們研究簡單的類比數位轉換器架構, 可以容易實現在不同光強度的環境裡輸入多個列陣信號轉換的應用。而隨著無限通訊系統和個人可攜式電子產品的爆發性成長，對於低功率、低電壓的積體電路有著不可或缺的需求。在今日許多的應用當中，大多使用數位信號處理技術來處理所傳輸的資料，因此，在接收到的類比訊號和數位信號處理系統間，需要一個將類比訊號轉換成數位訊號的介面。類比訊號轉換成數位訊號的介面既為整個系統的一部分，也同樣必須受到低功率、低電壓的限制。
在本論文中，以迴圈式類比數位轉換器為主體架構，電路包含了取樣保持電路、1.5位元子類比數位轉換器、2位元快閃式類比數位轉換器、乘法式數位類比轉換器，並使用數位錯誤更正技巧來避免電路中非理想誤差，例如：放大器的增益誤差與比較器的輸入偏移量等。此種架構除了可減少電路非理想誤差，還能利用控制迴圈的次數來達到不同需求的解析度。雖然轉換速度因為重複迴圈解析而造成輸出延遲，但卻能達到低功率、小面積與低成本的需求。本篇論文的模擬參數是採用 TSMC0352P4M 製程，以HSPICE為模擬軟體。

Recently, the display panel of portable devices is normally equipped with resistor array for hand writing signal input. In newly development, photo sensitive array has been successfully embedded in the panel and the image capture by through panel has been viable. In this research, we investigate an ADC that has simple structure and could be easily implemented with multiple input array signals in different light intensity environment. With the explosive growth of wireless communication systems and portable consumer electronics, the demand for low-power low-voltage integrated circuits (ICs) is indispensable. Many of the applications nowadays utilize the digital signal processing to resolve the transmitted information. Therefore, between the received analog signal and the DSP system, an analog-to-digital interface is required. Being apart of the system, the A/D interface also needs to adhere to the low-power low-voltage constraint.
In this paper, we use cyclic type ADC for subject frame which consists of sample-and-hold, 1.5bit/stage sub-ADC, 2bit Flash ADC, and Multiplying Digital-to-Analog Converter. It used Digital Error Correction Technique to avoid non-ideal circuit defects. For example: opamp gain error and comparator offset etc. This structure besides reduces non-ideal circuit defects, but also control the times of circle number to achieve the purpose of the different resolution. Although the conversion rate was slower, it could achieve low power, the small area and low cost demand. The circuit proposed above is design in a TSMC 0.35um process and verified by HSPICE program.

誌謝.......................................................I
摘要......................................................II
Abstract.................................................III
Content...................................................IV
Figure captions...........................................VI
Table captions............................................IX
Chapter
I   Introduction...........................................1
    1.1 Overview...........................................1
       1. Application of Sensor System.....................1
       2. Application of Communication Systems.............4
    1.2 Motivation.........................................6
    1.3 Thesis organization................................7
II   Review ADC............................................8
    2.1 Introduction.......................................8
    2.2 A/D Converter Characterization.....................8
       1. Resolution.......................................8
       2. Sampling Rate....................................8
       3. Signal to Noise Ratio............................9
       4. Nonlinearity....................................11
       5. Power Dissipation...............................14
    2.3 A/D Architecture..................................14
       1. Flash ADC.......................................14
       2. Two-Step ADC....................................17
       3. Pipelined ADC...................................18
       4. Time-Interleaved ADC............................20
       5. Cyclic ADC......................................21
III   Cyclic ADC circuit & analysis.......................23
    3.1 General Cyclic ADC Architecture...................23
       1. Key Building Blocks of Cyclic ADC...............24
       2. 1.5-Bit / Stage Architecture....................25
    3.2 Digital Error Correction Technique................27
    3.3 Input stage-Sample and Hold.......................30
       1. Switches........................................31
       2. Simple S/H......................................32
       3. Differential S/H circuit........................33
    3.4 Analog-to-Digital Sub-Converter (ADSC)............35
    3.5 Multiplying Digital-to-Analog Converter (MDAC)....36
    3.6 Amplifier.........................................39
    3.7 Comparator........................................40
    3.8 Digital Error Correction..........................43
IV   Simulation and Results...............................45
V   Conclusion and Future Work............................49
Reference.................................................50

                                

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