隨著網際網路技術發展與硬式磁碟機成本降低，磁碟陣列愈來愈普遍被使用，由作業系統模擬的軟體磁碟陣列是取得磁碟陣列最經濟的方式。目前大多數軟體磁碟陣列的實作大多是針對單核心處理器平台所設計，然而目前中央處理器的發展趨勢已從高工作時脈轉變成多核心，多核心處理器是否能為軟體磁碟陣列帶來更好的效能是一個值得討論的議題。利用多核心處理器的資源來執行預取技術已是一項熱門的議題，目的是減少迴圈中規律的快取失誤而提早將記憶體中資料擷取進入快取記憶體，進而提升效能。在某些應用中，存取磁碟的行為也存在著許多規律，是否也能利用多核心的來進行對磁碟的預先讀取，是本論文研究的主題，本論文中利用協助者執行序來紀錄使用者或執行序在使用資料上的習性，進而預先讀取資料，目的在於減短等待資料的時間甚至於整體執行時間。實驗結果顯示，在適當的參數調校之下的確可以增進讀取以及整體效能。

As the cost of hard disks decreases, it has become more common for people to use RAID. The RAID provides higher performance or higher security to users. Software RAID is the most economical way to own a RAID. Today, most processors of home and business computers are sufficient to provide this processing power. The developing trends of processors are “Multi-core” now. Hence, the software RAID runs on multi-core processors should be a trend in the future. However, most software RAID implementations are designed for single-core processor and the implementations do not utilize the power of the multi-core processor properly. The performances of the systems that access disks frequently are limited by the storage systems. In order to reduce the bottleneck, we should utilize the power of multi-core processor to enhance the performance of the storage system. In this thesis, we propose a prefetching mechanism on the multi-core software RAID. We use the multi-core processor and the high speed main memory to enhance the performance of reading on a RAID. All our designs are implemented in a helper thread and the helper thread will dynamically profile the user’s behavior and prefetch possible data. The simulation results demonstrate that our design can enhance the performance of read operator on a system that a data have high correlation between other data.

[1] Shameem Akhter and Jason Robert: “Multi-Core Programming”, Intel PRESS
[2] Daniel P. Bovet & Marco Cesati: “Understanding the Linux kernel,3e” , O’REILLY
[3] J.A.Brown, H. Wang, G. Chrysos, P. H. Wang, and J.P. Shen. “Speculative Precomputation on Chip Multiprocessors,” in Proc. of MTEAC-6, Nov 2002.
[4] Rudolf Bayer, Edward M. McCreight: Organization and Maintenance of Large Ordered Indices. Acta Informatica 1: 173-189 (1972)
[5] Corbet, Rubini and Kroah-Hartman: “Linux Device Driver, 3e”, O’REILLY
[6] G. K. Dorai, D. Yeung. “Transparent Threads: Resource Sharing in SMT Processors for High Single Thread Performance,”In Proc. of PACT-2002, Sept 2002.
[7] D. Kim, S. S. Liao, P. H. Wang, J. d. Cuvillo, X. Tian, X. Zhou, H. Wang, D. Yeung, M. Girkar, J. P. Shen,“Physical Experimentation with Prefetching Helper Threads on Intel’s Hyper-Threaded Processors,”In Proc. of CGO’04, March 2004.
[8] Jiwei Lu, Abhinav Das, Wei-Chung Hsu, Khoa Nguyen, Santosh G. Abraham:“Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor” 2005
[9] S. S. W. Liao, P. H. Wang, H. Wang, G. Hoflehner, D.Lavery, and J. P. Shen. “Post Pass Binary Adaptation for Software Based Speculative Precomputation,” in Proc. of PLDI’02, Jun 2002.
[10] P. H. Wang, J. D. Collins, H. Wang, D. Kim, B. Greene, K.-M. Chan, A. B. Yunus, T. Sych and J. P. Shen. “Helper Threads via Virtual Multithreading On an Experimental Itanium 2 Machine”, in Proc. of ASPLOS-XI, Oct 2004.
[11] Wikipedia. The information of DDR http://en.wikipedia.org/wiki/DDR
[12] Wikipedia. The information of DDR2 http://en.wikipedia.org/wiki/DDR2
[13] Wikipedia. The information of DDR3 http://en.wikipedia.org/wiki/DDR3
[14] Wikipedia. The information of SATA http://en.wikipedia.org/wiki/SATA
[15] Wikipedia. The information of SCSI http://en.wikipedia.org/wiki/SCSI
[16] Y. Solihin, J. Lee, and J. Torrellas. “Using a User-Level Memory Thread for Correlating Prefetching,” in Proc. of ISCA-29, May 2002.